Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-07-11
2002-12-17
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06496133
ABSTRACT:
FIELD OF INVENTION
This invention relates generally to an integrated circuit including a resistor string and to a method for its manufacture, and more specifically to a resistor string integrated circuit having reduced linearity error and to a method for reducing the linearity error of a resistor string integrated circuit.
BACKGROUND OF THE INVENTION
Some integrated circuits (ICs) such as digital to analog converters (DACs) and analog to digital (ADCs) converters use a resistor string to provide a plurality of comparator reference voltages. The resistor string includes a plurality of resistors, ideally identical unit resistors, coupled in series between two external reference voltages, a high reference voltage (V
rH
) and a low reference voltage (V
rL
). To implement an n-bit DAC, a string of 2
n
resistors is required. If the resistors are identical, by contacting the nodes between the 2
n
resistors, 2
n
+1 precisely known reference tap voltages (including the two external reference voltages) can be realized. In an 8-bit DAC, for example, 2
8
or 256 resistors are coupled in series to provide the DAC output voltages. Depending on the DAC input code, one of these tap voltages is directed to the output of the resistor string.
Unfortunately, it is not possible to produce a large number of identical resistors on an integrated circuit chip. Because of this, the 2
n
−1 internal tap voltages cannot be precisely known. Errors in resistor values, such as random and gradient errors, can accumulate as one moves from resistor to resistor along the resistor string between the two external reference voltages. This cumulative error results in an integral non-linearity (INL) error that, in turn, causes error in the output of the DAC.
Random errors in resistor values are caused, for example, by variations in the physical size of the resistors or by variations in the conductivity of the material from which the resistors are fabricated. These variations may be random or may be caused by gradients in processing variables. Gradient errors (which can be either linear or non-linear) are often addressed in IC layout and manufacture by interdigitating the affected components. With the large number of resistors commonly used in a resistor string, however, it is not practical to interdigitate all of the resistors. For practical layout reasons and to achieve some degree of interdigitation, resistor strings are often laid out in a plurality of columns of series connected resistors and the columns, in turn, are series connected.
For example,
FIG. 1
illustrates a prior art implementation of an 8-bit (256 resistor) resistor string
99
. Resistor string
99
includes 16 columns
101
-
116
of series coupled unit resistors. Each column includes 16 resistors such as resistors
121
-
136
in column
101
. Similar resistors are included in each of the other columns although the other resistors are not labeled with reference numbers. The illustrated placement of the columns matches the relative physical layout location of the columns as implemented in an integrated circuit embodiment. For example, column
102
is physically located between columns
101
and
103
. Although it is impractical to interdigitize all of the unit resistors to reduce gradient errors that may occur due to gradients in processing the resistors, it is possible to interdigitate the columns.
In accordance with this embodiment, the columns are connected in series by interconnecting column
101
to column
104
by a conductive interconnect
140
, column
104
to column
105
by a conductive interconnect
141
, column
105
to column
108
by a conductive interconnect
142
, column
108
to column
109
by a conductive interconnect
143
, column
109
to column
112
by a conductive interconnect
144
, column
112
to column
113
by a conductive interconnect
145
, column
113
to column
116
by a conductive interconnect
146
, column
116
to column
115
by a conductive interconnect
147
, column
115
to column
114
by a conductive interconnect
148
, column
114
to column
111
by a conductive interconnect
149
, column
111
to column
110
by a conductive interconnect
150
, column
110
to column
107
by a conductive interconnect
151
, column
107
to column
106
by a conductive interconnect
152
, column
106
to column
103
by a conductive interconnect
153
, and column
103
to column
102
by a conductive interconnect
154
. The end of column
101
is also coupled to a voltage reference terminal
156
that can be coupled to an external voltage reference supply (not illustrated) and the end of column
102
can be coupled to a second voltage reference terminal
158
that can be coupled to an external voltage reference supply (not illustrated).
A voltage reference tap point is provided at the node at each end of each of the unit resistors. For example, in column
101
voltage reference tap points
161
-
177
are provided at the ends of resistors
121
-
136
, respectively. Similar voltage reference tap points are provided (although not labeled with reference numbers) in each of the other columns. Switches
181
-
197
are coupled to voltage reference tap points
161
-
177
, respectively to selectively couple a voltage reference tap point to the output (not illustrated) of the resistor string circuit. Again, only the switches coupled to the voltage reference tap points in column
101
have been labeled with reference numbers.
Although this resistor string layout may address some of the gradient errors, it does not address the occurrence and effect of random errors. Further, a gradient from one end of the string to the other will create linearity errors. If the layout of the resistor string is one column of unit resistors or a string of sequentially connected columns of resistors, the linear gradient of the unit resistor values will produce a bow shaped linearity error, e.g., with the correct value at the ends coupled to the external reference voltages and maximum error in the center of the string, at the output of the string.
Moreover, it is not practical to trim the resistance of each of the 2
n
resistors in an integrated resistor string to a precise value. Because of the large number of components already required for the n-bit string, it is also not practical to add additional components (and hence increase the size of the IC) that might otherwise aid in reducing the linearity error. Accordingly, an integrated circuit and method are needed that can reduce linearity errors in an integrated resistor string but will not increase the complexity of processing the IC and will not increase the device count of the IC.
SUMMARY OF THE INVENTION
A resistor string integrated circuit and method according to the present invention addresses many of the problems of the prior art. In accordance with various aspects of the present invention, an improved resistor string integrated circuit having reduced linearity error and to a method for reducing the linearity error of a resistor string integrated circuit are provided.
In accordance with an exemplary embodiment of the invention, to reduce the linearity error that results from the processing of an integrated resistor string, the resistor string is implemented by forming a plurality of unit resistors coupled in series between two voltage reference terminals. The series coupled unit resistors are laid out in a plurality of columns, and the columns are intercoupled in groups of columns. The columns included in each of the groups of columns are suitably selected such that the total resistance of each group of columns is substantially the same. By grouping the columns so that each group of columns has substantially the same resistance, the linearity error is substantially zero at the ends of each of the groups and the linearity error of the entire string is reduced.
In addition, the resistor string integrated circuit and method can be configured with any number of resistors, columns and groups of columns. For example, the linearity of an n-bit integrated resistor string can be improved b
Brady W. James
Jeanglaude Jean Bruner
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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