Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-08-31
2001-04-24
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06222474
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to digital-to-analog converters, and are more particularly directed to converters using resistor strings.
A digital-to-analog converter (“DAC”) may be used in various types of electronic circuits, or itself may be formed in a single integrated circuit device. In operation, the DAC is used to convert an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. For further background, a DAC illustrated as having a resistor string in a single dimension may be seen in co-pending U.S. patent application Ser. No. 09/342,878, entitled “Bit Interpolation In A Resistor String Digital-To-Analog Converter”, filed Jun. 29, 1999, having the same inventors as the present application, and hereby incorporated herein by reference. However, the embodiments of this application pertain more favorably to a DAC having a meander resistor string and, thus, a description of a prior art system with such a string is described as further background immediately below.
FIG. 1
illustrates a typical configuration of a prior art DAC
10
, and is detailed briefly here with additional understandings left to one skilled in the art. By way of example and as appreciated later, DAC
10
is a 4-input 16-output DAC, while numerous other dimensions may exist for different DAC configurations. In general and as detailed below, DAC
10
is operable to receive a 4-bit input word, designated from least significant bit to most significant bit as I
0
-I
3
, and in response to the magnitude of that input, to output a corresponding analog voltage. Before detailing this operation, it is first instructive to examine the devices and connections of DAC
10
. In this regard, DAC
10
includes a series-connected resistor string designated generally at
12
, and which forms a meander in that it serpentines back and forth. Additionally, DAC
10
is generally an array in nature, having a number of bit lines in the vertical dimension and a number word lines in the horizontal dimension. Since the example of DAC
10
presents a 4-input 16-output DAC, the array of DAC
10
includes four bit lines designated BL
0
through BL
3
, and four word lines designated WL
0
through WL
3
. Also for the current example of a 4-to-16 DAC, resistor string
12
includes fifteen resistive elements shown as R
0
through R
14
. Resistive elements R
0
through R
14
may be formed using various techniques, where the particular technique is not critical to the present inventive teachings. Also in this regard, in an effort to maintain the linearity between the digital input and the analog output, a common concern in the art is to endeavor to ensure that each resistor in the string has as close to the same resistance value as all other resistors in the string. Moreover, a voltage source V
REF1
is applied across resistor string
12
, and may be of any suitable biasing voltage, which for current applications is typically on the order of 2 to 5 volts. In any event, given the equal resistance of each element in the string, the voltage division across the resistors is uniform.
Looking to the detailed connections with respect to the resistive elements in string
12
, each resistive element provides two taps from which a voltage may be measured as detailed below. For example, looking to resistive element R
0
, it provides a tap T
0
and a tap T
1
, while resistive element R
1
shares the same tap T
1
and provides another tap T
2
, and so forth. Each tap has a switching device connected between it and a corresponding output bit line. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which the drain of the transistor is connected. For example, the drain of transistor ST
0
is connected to tap T
0
, the drain of transistor ST
1
is connected to tap T
1
, and so forth. Further, the switching transistors are arranged so that a like number of taps are coupled via corresponding switching transistors to a corresponding one of the bit lines. In the current example of DAC
10
, four taps are coupled in this manner to a corresponding bit line. For example, taps T
0
through T
3
are coupled, via corresponding switching transistors ST
0
through ST
3
, to bit line BL
0
. As another example, taps T
4
through T
7
are coupled, via corresponding switching transistors ST
4
through ST
7
, to bit line BL
1
. Moreover, each bit line BL
0
through BL
3
is coupled via a respective column access transistor, CAT
0
through CAT
3
, to a column decoder
14
. More particularly and for reasons evident below, column decoder
14
is coupled to receive the two most significant bits (MSBs) of the 4-bit word input to DAC
10
, and in response column decoder
14
controls the gates of column access transistors CAT
0
through CAT
3
.
Returning now to switching transistors ST
0
through ST
15
, and given the array nature of DAC
10
, it is further appreciated that the switching transistors are arranged so that a like number of switching transistors are controlled, via connection to their gates, by a corresponding word line which is further connected to row decoder
16
. In the current example of DAC
10
, four switching transistors are coupled in this manner to a corresponding word line. For example, the gates of switching transistors ST
0
, ST
7
, ST
8
, and ST
15
, are coupled to word line WL
0
. As another example, the gates of switching transistors ST
1
, ST
6
, ST
9
, and ST
14
, are coupled to word line WL
1
. Lastly in this regard, and for reasons evident below, row decoder
16
is coupled to receive the two least significant bits (LSBs) of the 4-bit word input to DAC
10
(i.e., bits I
1
and I
0
), and also the least significant bit (“lsb”) of the 2 MSBs input to column decoder
14
(i.e., bit I
2
). In response to these bits, row decoder
16
controls the gates of switching transistors ST
0
through ST
15
. More particularly, each least significant bit I
0
and I
1
is coupled as an input to a corresponding exclusive OR gate EOG
0
and EOG
1
as a first input, while the second input of exclusive OR gates EOG
0
and EOG
1
is connected to receive the least significant bit of the MSBs input to column decoder
14
.
The operation of DAC
10
is now described, first in general and then more specifically through the use of a few examples. A 4-bit digital word is connected to inputs I
0
through I
3
and, ultimately causes signals to pass to column decoder
14
and row decoder
16
. Generally, row decoder
16
includes sufficient logic circuitry or the like to respond by enabling one of word lines WL
0
through WL
3
, thereby providing an enabling voltage to the gates of the four switching transistors coupled to the enabled word line. Similarly, column decoder
14
includes sufficient logic circuitry or the like to respond by enabling one of column access transistors CAT
0
through CAT
3
, thereby causing the enabled transistor to pass the voltage from the corresponding one of bit lines BL
0
through BL
3
to output V
OUT1
. In a simple case, the result of the above operations may be viewed by correlating the value of the 4-bit input to one of the sixteen decimal tap numbers. For example, if the 4-bit digital word equals 0001 (i.e., decimal value
1
), then through enabling a switching transistor and a column access transistor the voltage at tap T
1
is coupled to V
OUT1
.
By way of detailed illustration of the operation of DAC
10
, the example of an input equal to 0001 is now traced through DAC
10
in greater detail. From the input of 0001, its two MSBs are coupled to column decoder
14
and, thus, the value of 00 is received by column decoder
14
. In response, column decoder
14
enable
Fattaruso John W.
Mahant-Shetti Shivaling S
Neerings Ronald O.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Williams Howard L.
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