Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-12-21
2003-09-09
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S154000
Reexamination Certificate
active
06617989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a digital-to-analog converter and, more particularly, to a resistor string digital-to-analog converter.
2. Description of Related Art
String digital-to-analog converters (DAC) are a type of DAC that includes a plurality of resistors connected in series between a high and low supply voltage. Connecting nodes or tap points between the resistors are selectively switched to an output node in response to the digital input. The resistor string acts as a large voltage divider with each tap point of the string being at a different voltage value. A switch matrix selects one of the tap points to the output node depending on the digital word input to the DAC. The voltage of the tap point is a monotonic analog representation of the digital input.
Referring now to
FIG. 1
there is illustrated a prior art 3-bit resistor string DAC which consists of 2
3
or 8 resistors connected in series between two reference voltages. The lower node of each resistor is selectively switched by the switch matrix to the input of the output buffer in response to a decoded digital input word. Thus, the input voltage to the output buffer is the voltage drop across the associated resistive elements of the resistor string in which the voltage drop across each resistor is VRP-VRN/8.
Generally, an N-bit resistor string DAC consists of 2 resistors and the number of switches range from 2
N
to 2(2
N
)-2, depending on the complexity of the decoder. For example, a 10-bit DAC would require 1024 resistors and 1024 tap points with 1024 associated switches. This type of DAC, however, suffers from the spacing requirements. Because of the spacing requirement for such a large number of resistors and switches, this DAC arrangement is particularly impractical for eight bit applications and larger. Not only does the die area increase rapidly with the number of bits, but the speed is also limited by the parasitic capacitances associated with the large number of switches.
One approach to reduce the number of resistors and switches in a string DAC is described in U.S. Pat. No. 5,808,576, issued Sep. 15, 1998, entitled “Resistor String Digital-To-Analog Converter”. Here, the resistor string is partitioned into a most significant bit (MSB) portion and a least significant bit (LSB) portion in which the LSB portion comprises a pair of variable resistors with one located on the top portion of the MSB portion and the other located on the lower portion of the MSB portion.
In the 576 patent, the values of the resistor bank can be shifted up or down by switching in the variable resistors. However, the variable resistors are also realized as resistor banks. Although this approach offers significant advantages over the conventional approach, a superior DAC can be realized by isolating the MSB and LSB portions and by further reducing the number of resistors and associated switches.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a method and apparatus for converting an N-bit digital word to an analog voltage signal in which a first circuit provides for conversion of the most significant bits of the N-bit digital word and a second circuit provides for the conversion of the least significant bits. The first circuit includes an array of resistors coupled in series between reference nodes and a switch matrix for providing a node voltage to a first input of a buffer responsive to an indication of the most significant bits of the N-bit digital word in which the buffer output provides the analog voltage signal. The second circuit includes a current device electrically isolated from the resistors of the first circuit and coupled to a second input of the buffer in which the second input is coupled in a feedback arrangement with the buffer output. The current device is operable to provide a select current such that the resistance of the feedback loop and the current are cooperable to modify the analog voltage signal by an amount corresponding to the least significant bits of the N-bit digital word.
REFERENCES:
patent: 3857021 (1974-12-01), Wilensky et al.
patent: 4567463 (1986-01-01), Naylor
patent: 5448506 (1995-09-01), Tateno
patent: 5703588 (1997-12-01), Rivoir et al.
patent: 5808576 (1998-09-01), Chloupek et al.
patent: 5920273 (1999-07-01), Hirano
patent: 6225929 (2001-05-01), Beck
patent: 6400300 (2002-06-01), Leung et al.
patent: 6433717 (2002-08-01), Leung
Brady III Wade James
Jeanglaude Jean Bruner
Neerings Ronald O.
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