Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-04-14
2001-10-23
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06307495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuit digital-to-analog converter units that are based on voltage-dividing resistor chains. Addressing logic, responsive to a digital input word, selects a metal-oxide-semiconductor (MOS) switch. The selected switch has an input terminal coupled to a position on the voltage-dividing circuit chain, the selected position having a voltage level corresponding to the digital input word. The selected switch applies the voltage from the voltage dividing chain to an output terminal. This structure is used in FLASH digital-to-analog converters and in system architectures incorporating FLASH digital-to-analog converters.
2. Description of the Prior Art
A schematic circuit diagram of a digital-to-analog converter
10
is shown in
FIG. 1. A
series of resistors
11
′ provides a voltage-dividing resistor chain
11
. The resistor chain
11
provides a sequence of voltage levels between the resistors of the resistor chain. Switches
12
are positioned between each voltage level determined by the resistor chain and an output terminal
15
. A decoder unit
13
has a digital input signal group (or word) applied thereto. The decoder unit
13
provides an activation signal to the selected switch
12
having a voltage level applied to its input terminal that corresponds to magnitude of the digital input signal. The selected switch
12
applies this input voltage level to the output terminal
15
of the digital-to-analog converter unit. In this manner, a digital input signal is converted to a(n analog) signal voltage level V
OUT
corresponding to the input digital signal word.
Integrated circuit digital-to-analog converter units responsive to a small number of logic bits, such as 4 or 5 bits, can implement the resistor chain with a single straight path. The resistor elements are typically fabricated using poly-silicon or metal lines. However, when the digital-to-analog converter unit is responsive to a large number of digital bits, the implementing structure is similar to integrated circuit memory units. A two- or three-dimensional decoding structure can then be used to access the switch coupled to the voltage level corresponding to the digital input word. This digital-to-analog converter array requires a resistor path (or chain) that is laid out in a parallel, back-and-forth path generally referred to as the meander. Because the voltage-dividing chain requires a large number of resistive elements, the total length of the resistive path is long. A metal path is the best material choice for the implementation of a voltage-dividing chain with moderate power consumption and good frequency response.
The linearity of the digital-to-analog converter unit transfer characteristics relies on the uniformity of all the resistive elements forming the voltage-dividing chain. The resistive elements in each lateral straight run of the meander must be similar to the elements that result in the reversal of the meander path. One possible approach to this problem has been described in U.S. Pat. No. 5,534,862. This approach of this reference is to insure that every cell in the voltage divider chain and switch access point (straight run cells and endpoint cells) contains at least one right-angle bend in the metal trace forming the resistor chain. The direction reversal is then accomplished with relatively small resistor error by reorientation of the bend in the path. The cell area needed to implement this approach is larger than necessary because of process design rules for the fabrication of this converter unit structure. However, the size of the array should be minimized because the process gradients of material thickness and etching will result in resistor element mismatch from one side of the array to the other. This mismatch resulting in the overall integral non-linearity (INL) of the digital-to-analog converter will be improved if the array size can be reduced.
A need has therefore been felt for a voltage-dividing network for use with an integrated circuit digital-to-analog converter unit in which the each resistive element in the voltage-dividing network has substantially the same (resistive) value. The voltage-dividing network should provide the highest density of cells (that include the switching elements) and consequently, the minimum area in the integrated circuit for the digital-to-analog converter unit.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, by providing a voltage-dividing network that permits the array of switches coupled thereto to have a square geometry. The voltage-dividing network includes a resistive path having expanded or junction regions at locations along the path where the voltage levels are established. The expanded or junction regions are positioned at corners of the path meander and at positions on the non-corner or straight portions of the resistive path. These expanded or junction regions provide a chain of elements that have an equal resistance to the first approximation. In the preferred embodiment, the junction regions on voltage-dividing circuit provide the precision voltage levels for a digital-to-analog converter unit. The voltage levels on the resistive path can be made equal to a higher precision by providing trim portions on the expanded junction regions on the resistive path. The square geometry of the cells permits the voltage-dividing network and the associated switching elements to occupy a minimum area on the integrated circuit substrate.
These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.
REFERENCES:
patent: 4804940 (1989-02-01), Takigawa et al.
patent: 4929923 (1990-05-01), Dharmadhikari
Fattaruso John W.
Mahant-Shetti Shivaling S.
Brady III Wade James
Holmbo Dwight N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Williams Howard L.
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