Resistor-capacitor oscillator circuit

Details Resistor-capacitor oscillator circuit Resistor-capacitor oscillator circuit

2002-03-13

2003-07-08

Lam, Tuan T. (Department: 2816)

Oscillators

Phase shift type

C331S137000

Reexamination Certificate

active

06590464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention generally relates to an oscillator circuit, and more particularly, to a precise resistor-capacitor oscillator circuit that is not easily influenced by the process and temperature.
2. Description of Related Art
The oscillator is able to generate a square pulse having a fixed frequency, and is widely used in logic electronic circuitry. The traditional looped oscillator composed of the fixed resistor-capacitor (RC) is shown in FIG.
1
.
In
FIG. 1
, a current source
100
generates a current I=V
BG
/R according to the fixed resistor R, wherein the V
BG
denotes a stable voltage generated by a bandgap circuit. The bandgap current source
100
is in the conventional art, and thus will not be described in detail herein. The oscillator circuit generates an oscillating pulse signal in the output terminal Kout according to the resistor value of the current source
100
and the capacitance of the circuit.
One terminal of the current source
100
is grounded, whereas the other terminal is connected to the switch circuit of the oscillator, wherein the connection comprises a first path
102
a
and a second path
102
b
. The first path
102
a
and the second path
102
b
are symmetric and are connected in parallel. The first path
102
a
comprises a NMOS transistor and a PMOS transistor that are connected in serial. The source of the NMOS transistor is coupled to the current source
100
. The source of the PMOS transistor is coupled to a voltage source V ps. The junction node A where the NMOS transistor and the PMOS transistor are coupled is further coupled to a capacitor
104
a
, and then further coupled to a ground voltage. In order to prevent the influence from the system voltage Vcc, the voltage source Vps is output from a regulator
101
. Herein, the regulator is used to receive the system voltage Vcc and output the fixed voltage source Vps that is used by the oscillator.
The gate of the NMOS transistor and the gate of the PMOS transistor are jointly coupled, and further coupled to an output terminal Kout. Furthermore, the junction node A is further coupled to a Schmitter inverter
106
a
. The output terminal of the Schmitter inverter
106
a
is coupled to a NAND gate
108
a
. The output terminal of the NAND gate
108
a
is coupled to an inverter. The output terminal of the inverter is coupled to a NAND gate
110
a
. The output terminal of the NAND gate
110
a
is the signal output terminal Kout, and further fed back to the gate of the NMOS transistor and the gate of the PMOS transistor of the first path
102
a.
In order to obtain 50% signal pulse of the duty cycle, the second path
102
b
also comprises an NMOS transistor and a PMOS transistor that are jointly coupled in serial. The junction node B is also coupled to a capacitor
104
b
(the value is the same as
104
a
's) that is further coupled to the ground voltage. Moreover, the junction node B is connected to a Schmitter inverter
106
b
, a NAND gate
108
b
, an inverter and a NAND gate
110
b
. The NAND gate
108
a
and the NAND gate
108
b
receive the output from each other. Similarly, the NAND gate
110
a
and the NAND gate
110
b
also receive the output from each other.
According to the traditional circuit of
FIG. 1
, the voltage waveform of the junction node A and the junction node B are shown in FIG.
2
. The phase difference in between is 180 degrees. However, the waveform is the interleaved descending wave section and the stable high level. The high level is the voltage source Vps, and the low level is the trigger voltage of the Schmitter inverter
106
a
. The descending slope of the voltage on the capacitor is determined by the RC, and the transformation voltage of the descending edge is determined by the Schmitter inverter
106
a
and
106
b
. Therefore, the transformation voltage of the descending edge of the traditional circuit is easily influenced by the process and the temperature, so that the output frequency changes accordingly and a regulator circuit is demanded. Therefore, the complexity is increased.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a resistor-capacitor oscillator circuit. The resistor-capacitor oscillator circuit comprises two comparators, has a more simple circuit structure, and is not easily influenced by the process and the temperature of the system voltage Vcc. Furthermore, the resistor-capacitor oscillator also saves power consumption.
A resistor-capacitor oscillator circuit of the present invention is driven by a current source, and the resistor-capacitor oscillator comprises a first switch path and a second switch path. Wherein, the first switch path comprises a signal output terminal and a first voltage output terminal. The second switch path comprises a complementary signal output terminal and the second voltage output terminal. One of these two voltage output terminals is selected randomly and input to both the first comparator and the second comparator simultaneously. The first comparator further receives a ½ V
BG
voltage, and the second comparator further receives 2V
BG
voltage. The first comparator outputs to a PMOS transistor, and the second comparator outputs to a NMOS transistor. The PMOS transistor is in series with the NMOS transistor, and is jointly coupled in between the system power supply and the ground voltage. Moreover, a latch and an inverter are serially coupled to the location of the serial junction node of these two transistors. The output of the latch is coupled to the output terminal of the complementary signal, and the output of the inverter is coupled to the output terminal of the signal.
The present invention further provides a resistor-capacitor oscillator circuit that is driven by a current source. The current source has a stable output voltage V
BG
. The oscillator comprises a first switch circuit, a second switch circuit, a first comparator, a second comparator, and a third switch control circuit. The first switch circuit has a first signal output terminal and a first node, wherein the first signal output terminal outputs a first output pulse signal, and the first node is coupled to a ground voltage via a first capacitor. The second switch circuit is symmetric and coupled in parallel with the first switch circuit, and bears a second signal output terminal and a second node, wherein the second signal output terminal outputs a second output pulse signal that complementary with the first output pulse signal. The second node is coupled to the ground voltage via a second capacitor, and the capacitance of the first capacitor is equal to the capacitance of the second capacitor. The first comparator is coupled to a selected node of either the first node or the second node, and is used to receive a corresponding voltage of either the first voltage or the second voltage, and also to receive a fixed lower limit voltage value. The second comparator is coupled to the selected node, and is used to receive a fixed upper limit voltage value. The third switch control circuit receives the input of the first comparator and the input of the second comparator. Moreover, the two output terminals of the third switch control circuit are coupled to the first signal output terminal of the first switch circuit and the second signal output terminal of the second switch circuit respectively.


REFERENCES:
patent: 4652837 (1987-03-01), D'Arrigo et al.
patent: 5990753 (1999-11-01), Danstrom et al.
patent: 6100766 (2000-08-01), Segawa et al.

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