Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-05-01
2004-04-06
Mai, Son L. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S002000, C257S003000, C257S530000, C438S095000, C438S257000
Reexamination Certificate
active
06717234
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates generally to data storage devices, and, more particularly, to resistive memory elements and arrays for data storage devices.
2. Related Art
A resistive memory device is typically characterized by the capability of assuming one of two distinct resistance states at any one time. Data is stored in the device based on the resistance state of the device. Typically, a logic “1” is characterized by a high resistance, while a logic “0” is characterized by a low resistance.
A typical resistive memory device is an anti-fuse memory device. An anti-fuse memory device, as the name implies, functions in an opposite manner than a fuse. An anti-fuse device normally has a very high resistance, typically an open circuit, unless and until a voltage is applied to the device. When a sufficient voltage is applied to an anti-fuse memory device, the resistance of the device is reduced to a very low resistance, typically a short circuit. Like a blown fuse, once an anti-fuse memory device is shorted, it is typically impossible or impractical to cause it to open again. Therefore, anti-fuse memory devices are typically referred to as a write-once memory devices.
Resistive memory devices are typically arranged in a memory array. A typical resistive memory array is formed by a plurality of conductive traces arranged in rows and columns. The conductive traces extending along the rows of the array are generally referred to as “word lines” and the conductive traces extending along the columns of the array are generally referred to as “bit lines.” The word lines and bit lines are typically oriented in an orthogonal relationship to each other. A resistive memory device is formed at each intersection of a word line and a bit line. Each of the resistance memory devices in the array is capable of assuming one of two distinct resistance states, which are used to store information. Data is written into a device in the array by applying a voltage across the device.
Resistive memory devices are typically formed using integrated circuit processing techniques employing various combinations of material depositions, shape definitions using photolithography, and material removal (etches), as known to persons skilled in the art. As noted above, arrays of resistive memory devices are typically formed by arranging a plurality of generally parallel word lines in a generally orthogonal relationship with a plurality of generally parallel bit lines. Each of the word lines is of a generally uniform width, and is separated from the other word lines by a distance that is typically equal to the width of a single word line. Likewise, each of the bit lines is of a generally uniform width, and is separated from the other bit lines by a distance that is typically equal to the width of a single bit line. Arrays are typically symmetrical, and the bits lines and word lines are typically configured to have generally uniform widths.
The word lines are typically formed by depositing a layer of a metal conductor material, followed by a photolithography step to define the width of the lines and the distances between the conductors, followed by an etch step to remove the conductor material from the spaces between the lines. The bit lines are typically formed in the same fashion, and then are disposed orthogonally to the word lines. Since a resistive memory device, such as an anti-fuse, is formed at each intersection of a word line and a bit line, it is desirable to configure the widths of the word lines and bit lines as narrowly as possible to increase the density of resistive memory devices in an array.
Unfortunately, the size of each of the resistive memory devices in such an array is limited by the minimum width of the conductive traces (word lines and bit lines) which form the memory devices. The width of the conductive traces is limited by the capability of the photolithography technology used to form the conductive trace. Therefore, the density of the array (i.e., the number of resistive memory devices in an array of a given size) is also limited by the width of the conductive traces used to form the array.
SUMMARY
An exemplar resistive memory element comprises a first conductive structure and a second conductive structure, each of the conductive structures having a width of less than 1&lgr;, anti-fuse material on each conductive structure, and conductive material on the anti-fuse material such that anti-fuse material is interposed between each conductive structure and the conductive material.
An exemplar method for making a resistive memory element includes the steps of providing a generally plateau-shaped insulating structure, the insulating structure having a first side wall, a second side wall and a central region disposed between the side walls, depositing a first conductive material on the insulating structure, removing the first conductive material from the central region of the insulating structure to form a first conductor on the first side wall of the insulating structure and a second conductor on the second side wall of the insulating structure, depositing anti-fuse material on the first conductive material and on the central region of the insulating strucuture, and depositing a second conductive material on the anti-fuse material.
REFERENCES:
patent: 5625200 (1997-04-01), Lee et al.
patent: 6613604 (2003-09-01), Maimon et al.
patent: 2002/0017701 (2002-02-01), Kiersy et al.
Johnson Steven C.
Perner Frederick A.
Van Brocklin Andrew L.
Mai Son L.
Tran Long
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