Resistive ladder, summing node circuit, and trimming method...

Details Resistive ladder, summing node circuit, and trimming method... Resistive ladder, summing node circuit, and trimming method...

2005-04-19

2005-04-19

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S156000

Reexamination Certificate

active

06882294

ABSTRACT:
A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66and68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156and158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal.The invention also includes a method for trimming the subranging ADC. The novel method (250) includes the steps of trimming the complementary current sources of the coarse quantizer to match each other (252), trimming each of the DAC cells on one of the complementary DACs (254), trimming the overall DAC gain to match the gain of the coarse quantizer (256); and trimming the gain of the fine quantizer to match one coarse quantization Q level (260).

REFERENCES:
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patent: 5973631 (1999-10-01), McMullen et al.
patent: 6437724 (2002-08-01), Nagaraj

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