Static information storage and retrieval – Read only systems
Reexamination Certificate
2002-04-30
2003-07-22
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read only systems
C365S097000, C365S100000
Reexamination Certificate
active
06597598
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to resistive cross point memory cell arrays and, more particularly, the present invention relates to a resistive cross point memory cell array having a differential sense amplifier that utilizes a charge injection mode.
Many different resistive cross point memory cell arrays have been proposed, including resistive cross point memory cell arrays having magnetic random access memory (MRAM) elements, phase change memory elements, poly-silicon memory elements, and write-once (e.g., fuse based or anti-fuse based) resistive memory elements.
A typical MRAM storage device, for example, includes an array of memory cells. Word lines may extend along rows of the memory cells, and bit lines may extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line. Each MRAM memory cells stores a bit of information as an orientation of a magnetization. In particular, the magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of 0 and 1. The magnetization orientation affects the resistance of a memory cell. For example, the resistance of a memory cell may be a first value, R, if the magnetization orientation is parallel, and the resistance of the memory cell may be increased to a second value, R+&Dgr;R, if the magnetization orientation is changed from parallel to anti-parallel.
In general, the logic state of a resistive cross point memory cell may be read by sensing the resistance state of the selected memory cell. Sensing the resistance state of a single memory cell in the array, however, typically is difficult because all of the memory cells in a resistive cross point memory cell array are interconnected by many parallel paths. The resistance that is seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other word lines and bit lines.
Thus, one hurdle that must be overcome before high density and fast access resistive cross point memories may be developed is the reliable isolation of selected resistive cross point memory cells while data stored on a selected memory cell is being sensed. In general, prior techniques for isolating such memory cells fall into one of three memory cell isolation categories: select transistor isolation techniques; diode isolation techniques; and equipotential isolation techniques.
Known transistor isolation techniques typically involve inserting a select transistor in series with each resistive cross point memory cell. This architecture typically is characterized by fast read access times. Unfortunately, such series transistor architecture typically also is characterized by relatively poor silicon area utilization because the area under the resistive cross point memory cell array typically is reserved for the series transistors and, therefore, is unavailable for support circuits. In addition, this isolation technique also tends to suffer from relatively poor memory cell layout density because area must be allocated in each memory cell for a via that connects the memory cell to the series transistor in the substrate. This isolation technique also generally requires relatively high write currents because an isolated write conductor must be added to the memory cell to provide a write circuit in parallel with a read circuit and the location of the write conductor results in high write currents to generate the required write fields. In general, this approach is limited to a single memory plane because the series transistors must be located in the substrate and there is no practical way to move the series transistors out of the substrate and into the memory cell plane.
Diode isolation techniques typically involve inserting a diode in series with each resistive cross point memory element. This memory cell array architecture may be implemented with thin film diodes that allow multi-level resistive cross point memory arrays to be constructed (see, e.g., U.S. Pat. No. 5,793,697). This architecture has potential for high-speed operation. The difficulty often associated with this architecture involves providing a suitable thin film diode with minimum process feature sizes matching the potential density of the memory cell arrays. In addition, this approach uses one diode per memory element and, at currently practical MRAM features and parameters, for example, each diode would be required to conduct 5 to 15 kA/cm
2
. Such high current densities generally are impractical for implementing thin film diodes in high-density MRAM arrays.
Equipotential isolation techniques typically involve sensing resistive cross point memory cells without using series diodes or transistors (see, e.g., U.S. Pat. No. 6,259,644). This approach may be implemented by a cross point array of memory elements that is relatively simple to fabricate. This cross point memory cell array architecture typically has a density that is limited only by the minimum feature sizes of the implementing circuit technology and typically requires relatively low write currents. In addition, it is relatively simple to extend this approach to multi-level resistive cross point memory cell arrays to achieve very high-density memories. Equipotential isolation, however, often is difficult to implement in large arrays. Auto-calibration and triple sample read techniques have been used to sense data in large MRAM arrays using equipotential isolation techniques, but these sense processes typically limit the read sense time to a few micro seconds.
SUMMARY OF THE INVENTION
In one aspect, the invention features a data storage device that includes a resistive cross point array of memory cells, a plurality of word lines, and a plurality of bit lines, wherein a group of memory cells are connected to a common word line and each memory cell in the group is connected to a single bit line. A differential sense amplifier is coupled to the memory cell array and includes a first node selectively connected to a reference cell and a second node selectively coupled to a sense cell within the group of memory cells common to a given word line. A first preamplifier is connected to the first node, and a second preamplifier is connected to the second node. A charge injection amplifier is coupled to outputs of the first and second preamplifiers and is operable to determine a resistive state of the sense cell.
The memory cells may be arranged into multiple groups of one or more memory cells. The charge injection amplifier determines whether a sensed memory cell is in a first or second resistive state as compared to a reference cell. The charge injection amplifier may further comprise a comparator circuit that is coupled to an associated read circuit. The comparator circuit preferably is operable to convert an analog differential sense current to a digital output read signal.
In another aspect of the invention, an information storage device has a memory cell array with a plurality of sense cells and reference cells, each sense cell and reference cell having multiple states, a plurality of word lines, a plurality of bit lines and a differential sense amplifier, coupled to the memory cell array. The differential sense amplifier comprises first and second input nodes, the first input node being selectively coupled to a sense bit line connected to a selected sense cell within the array and the second input node selectively coupled to a reference bit line connected to a selected reference cell within the array. A first preamplifier is coupled to the first input node and has an output providing a first current representative of a state of the selected sense cell. A second preamplifier is coupled to the second input node and has an output providing a second current representative of a state of the selected reference cell. A charge injection amplifier is coupled to the output of the first preamplifier and the output of the second preamplifier, and
Perner Frederick A.
Tran Lung T.
Hewlett--Packard Development Company, L.P.
Phan Trong
LandOfFree
Resistive cross point memory arrays having a charge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Resistive cross point memory arrays having a charge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Resistive cross point memory arrays having a charge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3080689