Resistance multiplier circuit and compact gain attenuator

Details Resistance multiplier circuit and compact gain attenuator Resistance multiplier circuit and compact gain attenuator

2006-03-14

2006-03-14

Sircus, Brian (Department: 2836)

Electrical transmission or interconnection systems

Plural load circuit systems

Control of current or power

C330S256000

Reexamination Certificate

active

07012343

ABSTRACT:
A resistance multiplier circuit coupled to a first node of a first circuit for providing a high-value resistance at the first node includes a first transistor, a second transistor being N times larger than the first transistor, and a resistor. In one embodiment, the first and second transistors are NPN bipolar transistors. The first transistor has its base and collector terminals coupled to the first node and an emitter terminal coupled to a second node. The second transistor has a base terminal coupled to the first node, a collector terminal coupled to a positive supply voltage, and an emitter terminal coupled to the second node. The resistor is coupled between the second node and a virtual ground node. When a voltage is applied to the first node, the resistance at the first node is (N+1) times the resistance of the resistor.

REFERENCES:
patent: 5471173 (1995-11-01), Moore et al.
patent: 5734295 (1998-03-01), Kagawa
patent: 2004/0251965 (2004-12-01), Ueda et al.
De Veirman, G.A. The VLSI Handbook, 2000, CRC Press LLC, Chapter 20, pp. 15-16.

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