Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-08-28
2004-06-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000, C323S315000
Reexamination Certificate
active
06747508
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a resistance equivalent circuit, and more particularly, to an equivalent circuit of resistance mirror consisting of current mirror circuits and a mirror resistor set.
DESCRIPTION OF THE PRIOR ART
In general, to modulate the electrical characteristics of analog integrated circuits is usually by means of the resistance, capacitance or inductance adjustment. Among of them the most preferably is conducted, by adjusting the resistance for its simple, common, low cost and easy to handle.
Whereas, to achieve a specified function, for example, tuning the central frequency of multistage band pass filter circuit systems and/or sub-systems from one position to another, each sub-system should have a consistent modulation. However, if it is done by individually adjusting each resistor of the system, It would be time consuming and detrimental to the precision of the system, even more causes the circuit failed. Therefore, to overcome above-mentioned drawbacks, it is desired to have a new circuit technique for band-pass circuit that a resistance mirror circuit contains a master resistor and slave resistors. The latter is then controlled in accordance with a resistance change of the master resistor.
The object of the present is thus to provide such desired circuit.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a resistance mirror circuit having a set of adjustable resistors in accordance with a master resistance to meet different requirement of circuit application.
The present invention disclosed a resistance mirror circuit having a set of adjustable resistors with resistance in accordance with a master resistor. In the first preferred embodiment, the circuit comprises: (1) a master resistor R
0
, (2) a reference current source terminal providing a current value I
0
through the master resistor R
0
to ground;(3) a first transistor; (4) a current mirror source terminal providing a current value nI
0
, through the first transistor to ground; (5) an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R
0
, and an output terminal connecting to a gate of the first transistor; (6) a mirror resistor set consisting of a plurality of transistors in parallel each other and having their source electrodes connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers. Since gates of the transistors connect to the output terminal of the operational amplifier, each of the transistors therefore has an equivalent resistance R
eq
=(1
m)R
0
.
The second embodiment according to the present invention comprises: (1) a master resistor having resistance R
0
; (2) a first transistor, having a ratio of channel width over channel length thereof equal to W/L; (3) a reference current source terminal providing a reference current I
0
, the reference current being through first transistor, and the master resistance R
0
to ground; (4) a second transistor, having a ratio of channel width over channel length thereof equal to nW/L; (5) a third transistor having a ratio of channel width over channel length thereof equal to W/L; (6) a current mirror source terminal providing a mirror current value of nI
0
, in series connecting with the second transistor, the third transistor to ground, wherein the second transistor has a gate electrode connecting to a drain electrode, therefore the second transistor has the same current density and V
GS
voltage as the first transistor, where V
GS
voltage is voltage of the gate electrode to source electrode; (7) a mirror resistor set consisting of a plurality of transistors in parallel and with their source electrode connecting to ground, and each transistors having a ratio of channel width over channel length thereof equal to m W/L, wherein m are positive number; (8) an operational amplifier having a positive terminal connecting to a drain and a gate electrode of the second transistor, and output a signal to a gate of the third transistor and all gate electrodes of the transistors of the mirror resistor set; (9) a reference signal controlling a gate bias of said first transistor and feeding to a negative terminal of said operational amplifier so that a voltage across the master resistor R
0
is equal to the source voltage of the second transistor, therefore, each transistor of the mirror resistor set has an equivalent resistance R
eq
=(1
m)R
0
.
The transistors in the present invention are not limited in depleted mode transistors or enhanced transistors.
REFERENCES:
patent: 5107199 (1992-04-01), Vo et al.
patent: 5291123 (1994-03-01), Brown
patent: 5572161 (1996-11-01), Myers
patent: 6353344 (2002-03-01), Lafort
Chuang Chao-Hsuan
Fan Cheng-Hsuan
Hwang Kent
Liu Jing-Meng
Cunningham Terry D.
Richtek Technology Corp.
Tra Quan
Troxell Law Office PLLC
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