Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Integrated structure
Reexamination Certificate
2003-03-07
2004-05-18
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Integrated structure
Reexamination Certificate
active
06737912
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resistance division circuit and a semiconductor device and, more particularly, to the resistance division circuit and the semiconductor circuit using a MIS transistor as a resistive element.
2. Description of the Related Art
It is generally performed in a semiconductor device to generate a reference voltage for a power control circuit or the like by its resistance division while very small current flows a resistive element having high resistance (
FIG. 16
) or to generate a comparison voltage for a voltage monitor while very small current flows through a resistive element having high resistance (FIG.
17
). Specifically, in
FIG. 16
, a resistive element R
1
and a resistive element R
2
each of which has high resistance are connected in series between power voltage VDD and the ground, and a voltage is drawn from between the resistive element R
1
and the resistive element R
2
to generate the reference voltage. On the other hand, in
FIG. 17
, a P-channel MOS transistor P
1
and a resistive element R
3
and a resistive element R
4
, each of which has high resistance, are connected in series between power voltage VDD and the ground. Further, an amplifier OP, to which reference voltage VREF and the comparison voltage between the resistive element R
3
and the resistive element R
4
are inputted, is provided, and then output of this amplifier OP is inputted into a gate terminal of the P-channel MOS transistor P
1
. This allows to draw out a voltage from between the P-channel MOS transistor P
1
and the resistive element R
3
, thereby an output voltage is generated.
In a reference voltage generating circuit shown in FIG.
16
and an output voltage generating circuit shown in
FIG. 17
, a through current passes from the power voltage VDD to the ground, which directly causes an increase in current consumption in accordance with the through current. Therefore, in a path or the like that requires the through current also in a standby mode, reduction in power consumption becomes more important than a current driving force, so that it is sometimes desired to pass the through current as little as possible. Practically in this case, a current value may be reduced to about 100 nA or below. Suppose that a power source level is, for example, 1.8 V, it is required to have a resistive element having a high resistance value of 18 M&OHgr; in order to reduce the current down to 100 nA.
Conventionally, a polysilicon layer formed on a semiconductor substrate and an impurity diffused layer formed in the semiconductor substrate are used for the resistive element having such high resistance. Additionally used is such on-resistance that passes from an input terminal of a MOS transistor to an output terminal thereof when the MOS transistor is set to an ON-state.
Typical sheet resistance is several dozens &OHgr;/□ when forming the resistive element having high resistance with the polysilicon layer and the impurity diffused layer. Therefore, for example, forming the above-mentioned resistive element of 18 M&OHgr; by 30 &OHgr;/□ results in 600000 sheets, that is, 600000-fold length (in this case, 300000 &mgr;m=0.3 m) against width of a resistance layer (for example, 0.5 &mgr;m), which is not realistic in terms of an occupied area alone. Therefore, resistance realized by using the polysilicon layer and the impurity diffused layer is limited in such a case as that the current can flow with a little less resistance.
As described above, the resistive element having high resistance of about megohm requires a polysilicon layer and an impurity diffused layer in which impurity concentration is decreased to intentionally increase the resistance value. This can be achieved in an impurity implantation process by first masking regions except for a region in which the resistive element is formed, and then implanting impurities thereon with different concentration from other regions. This particular process, however, involves a problem that a process cost in the semiconductor device may increase.
In a case where a process of forming an impurity diffused layer having low concentration, which is used in an LDD structure, can be directly applied to a process of forming the resistive element, the sheet resistance becomes hundred to thousand times as high a value as a resistance value obtained when a normal impurity diffused layer is used. This enables to avoid an increase in the process cost, but it is undeniable that this resistive element still occupies considerable area on the semiconductor substrate.
Further, a recent salicide technology has developed to attach a layer having low resistance on the polysilicon layer and the impurity diffused layer. This involves a problem that the low resistance layer is similarly attached to the above-mentioned impurity diffused layer having the low concentration, which results in lowering the sheet resistance. In addition, when the salicide technology is set as a standard process, such a particular process is further required as to avoid salicide-forming only on a portion of the resistive element having high resistance, or to remove the formed salicide layer.
On the other hand, in a case of realizing high resistance by the on-resistance of the MOS transistor, current is reduced by narrowing down channel width W and by having gate length L rather long to set a W/L small. However, the on-resistance of a normal MOS transistor has about several K ohms per the channel width, so that realizing high resistance of 18 M&OHgr; results in setting the gate length L to unrealistic length.
An increase in resistance may also be realized by setting a gate voltage to a voltage that barely manages to conduct the MOS transistor to reduce the current. In order to generate this gate voltage, however, a circuit for generating an intermediate voltage is separately required.
SUMMARY OF THE INVENTION
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a resistance division circuit, comprises:
a first MIS transistor having a first gate terminal, a first source terminal, a first drain terminal and a first back gate terminal, wherein the first gate terminal is regarded as a first terminal, and the first source terminal, the first drain terminal and the first back gate terminal are regarded as a second terminal, and one of the first terminal and the second terminal is connected to a first node of a first voltage; and
a second MIS transistor having a second gate terminal, a second source terminal, a second drain terminal and a second back gate terminal, wherein the second gate terminal is regarded as a third terminal, and the second source terminal, the second drain terminal and the second back gate terminal are regarded as a fourth terminal, and one of the third terminal and the fourth terminal is connected to the other of the first terminal and the second terminal and the other of the third terminal and the fourth terminal is connected to a second node of a second voltage.
According to another aspect of the present invention, a semiconductor device including a first MIS transistor and a second MIS transistor, wherein
the first MIS transistor comprises:
a first well region formed in a surface side of a semiconductor substrate, the first well being connected to one of a first node of a first voltage and an output node;
a first source region formed in the surface side of the first well region, the first source region being connected to the one of the first node and the output node;
a first drain region formed in the surface side of the first well region, the first drain region being connected to the one of the first node and the output node; and
a first gate electrode formed on the first well region between the first source region and the first drain region via a first insulating film, the first gate electrode being connected to the other of the first node and the output node, and
the second MIS transistor comprises:
a second well region formed in
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Zweizig Jeffrey
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