Resist mask for measuring the accuracy of overlaid layers

Details Resist mask for measuring the accuracy of overlaid layers Resist mask for measuring the accuracy of overlaid layers

2002-07-17

2003-05-13

Powell, William A. (Department: 1765)

Adhesive bonding and miscellaneous chemical manufacture

Differential fluid etching apparatus

With measuring, sensing, detection or process control means

C156S345290, C438S737000

Reexamination Certificate

active

06562188

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a measurement mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, and also to a method of forming the measurement mark formed on the semiconductor wafer.
2. Description of the Related Art
To form circuit patterns on a silicon substrate, a photomask on which the circuit patterns are drawn is disposed on the silicon substrate, and then the circuit patterns on the mask are transferred onto a resist film formed on the silicon substrate by using conventional lithograph technology. Then, the circuit patterns are formed using conventional etching, with the patterned resist film serving as an etching mask. This lithographic process requires the accurate alignment of the photomask and the silicon substrate. To perform an accurate alignment, an alignment pattern formed on the photomask is overlaid on an alignment mark that is formed on the silicon substrate.
The accuracy of the alignment is measured by a resist mark having several measurement marks. Referring to
FIG. 1A
, an alignment mark
1
are formed on an alignment mark area
10
and a first measurement mark
2
are formed on a measurement area
20
of the silicon substrate
3
using the first photomask
4
. Then, a resist layer is formed on the entire surface of the silicon substrate
3
. After that, referring to
FIG. 1B
, an insulating layer
9
, such as silicon oxide layer is formed on the entire surface of the silicon substrate
3
, and then, an resist film is formed on the insulating layer
9
. After that, an alignment pattern
5
formed on a second photomask
6
is overlaid on the alignment mark
1
on the silicon substrate
3
by detecting an edge of the alignment mark
1
, and then, a conventional lithographic process is performed. As a measurement pattern
7
is formed on the second photomask
6
, a measurement mark
8
is formed by transferring the measurement pattern
7
into the resist film. As a distance between facing sides of the measurement pattern
7
is longer than a distance between facing sides of the first measurement mark
2
, an edge
40
of the first measurement mark
2
is encompassed by an edge
30
of the second measurement mark
8
. A value of the dislocation of the second photomask is measured by detecting the location of the edges
30
,
40
of the first and second measurement mark
2
,
8
.
In the process for forming the second measurement mark
8
, a thermal treatment is performed at over 100° C. for the second measurement mark
8
in order to reduce an organic solvent remained excessively in the second measurement mark
8
or to stiffen the second measurement mark
8
by a bridge-building reaction of macromolecules. In the performance of the thermal treatment, the second measurement mark
8
is deformed at its edge
30
by a phenomenon generally known as the “thermal flow”. Specifically, the deformation of the second measurement mark
8
at its edge
30
occurs if the distance between the facing sides is long because a large stress is applied to the second measurement mark
8
.
As the measurement of the dislocation using the deformed edge is not accurate, the alignment of another photomask in the subsequent process also is not accurate.
As a result, a defective circuit will be manufactured.
SUMMARY OF THE INVENTION
An objective of the invention is to resolve the above-described problem and to provide a resist mark having measurement marks which are not affected by the thermal flow phenomenon and which improve the alignment accuracy.
Another objective of the invention is to provide a method for forming a resist mark having features described above.
To achieve these objectives, a resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon. Further, the resist mask further includes a fourth measurement mark formed in an area which is surrounded by the second measurement mark. Still further, the second measurement mark is connected to the third measurement mark at its corners.
These objectives are further achieved by a method for manufacturing a semiconductor wafer having a resist mark for measuring the accuracy of overlay of a photomask disposed on the semiconductor wafer, the method including (a) forming a first layer on the semiconductor wafer, (b) forming a first rectangularly shaped opening in the first layer to make a first measurement mark, (c) forming an intermediate layer on the first measurement mark and in the first opening, (d) forming a second layer on the intermediate layer, (e) forming a second measurement mark and a third measurement mark by forming a second rectangularly shaped opening and a frame-shaped opening in the second layer, the second rectangularly shaped opening being located above the first opening, the second measurement mark being isolated form the third measurement mark by the frame-shaped opening, (f) wherein the second measurement mark is formed in a frame shape, and (g) wherein the second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.


REFERENCES:
patent: 4632724 (1986-12-01), Chesebro et al.
patent: 5952247 (1999-09-01), Livengood et al.
patent: 6274393 (2001-08-01), Hartswick
patent: 6368980 (2002-04-01), Minami et al.
patent: 6440262 (2002-08-01), Minami et al.
patent: 4-159706 (1992-06-01), None
patent: 8-17718 (1996-01-01), None

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