Resin-encapsulated semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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C257S676000, C257S686000, C257S692000, C257S693000, C257S783000

Reexamination Certificate

active

06552418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a resin-encapsulated semiconductor device comprising a resin integrally encapsulating a plurality of semiconductor chips including at least a center pad semiconductor chip in order to increase the integration capacity and improve the function and to a resin-encapsulated semiconductor device using a thin, compact and inexpensive lead frame.
2. Description of the Related Art
In recent years, various electronic devices have come to have their function improved and size and weight reduced remarkably and hence there has been a strong demand in the field of art for semiconductor devices to be incorporated into such electronic devices whose package has a smaller thickness and size as well as increased storage capacity, improved function and higher integration density. To meet this demand, a semiconductor device produced by a so-called multi-chip package technique has been proposed, according to which two semiconductor chips are integrally encapsulated with resin. As an example, Japanese Utility Model Laid-Open No. 6-2713 discloses a resin-encapsulated semiconductor device produced by rigidly placing at least two semiconductor chips perpendicularly to one another with insulator therebetween on a die pad and electrodes provided in the same direction, and connecting the electrodes of the semiconductor chips and leads provided in four directions with a metal wire, followed by encapsulation with resin mold. Japanese Patent Laid-Open No. 5-121462 discloses a resin-encapsulated semiconductor device produced by placing a first semiconductor chip on the side of a first surface of a semiconductor chip placing portion and a second semiconductor chip on the side of a second surface of the semiconductor chip placing portion, followed by wire bonding and resin encapsulation. Japanese Patent Laid-Open No. 11-163255 discloses an LOC type, resin-encapsulated semiconductor device having two semiconductor chips therein produced by placing two center pad type semiconductor chips each having electrodes in the center of a surface thereof and their back surfaces opposing one another, branching an inner lead into two branches, one of which is secured to a surface of one semiconductor chip with an insulating film therebetween, while the other branched inner lead is secured to the other surface of the semiconductor chip with an insulting film therebetween, followed by integral resin encapsulation as the tip end portion of each inner lead is connected with an electrode of each semiconductor chip with a Au wire.
However, the two semiconductor chips used according to the invention as disclosed by Japanese Utility Model Laid-Open No. 6-2713 and Japanese Patent Laid-Open No. 5-121462 each have electrodes provided in the vicinity of the periphery of the semiconductor chip. If the capacity of the semiconductor device is to be increased, the semiconductor chip size is inevitably large if the package size is restricted to be small. However, if electrodes are provided around the semiconductor chip, the increase in the size of the semiconductor chip is limited because a prescribed length should be secured for the inner lead. Furthermore, if the tip end of the inner lead is to be provided as close as possible to the semiconductor chip in order to secure a long size for the inner lead, the metal wire is in contact with the edge of the semiconductor chip, and in order to avoid the problem, the height of the bonding wire must be increased, which leads to increase in the package thickness. More specifically, in the resin-encapsulated semiconductor device according to the structure as disclosed by the document, if the two-dimensional size and the thickness of the package are limited, too much restriction is imposed in increasing the capacity of the semiconductor device, so that the capacity cannot be greatly increased.
According to the invention as disclosed by Japanese Patent Laid-Open No. 11-163255, center pad type, semiconductor chips allow the occupying area in a package and the capacity to be readily increased, which is advantageous for increasing the capacity, while a complicated structure results in which an inner lead is secured to the surface of the semiconductor chips through an insulating film, so that the material and assembling costs could be high. Particularly, in terms of facility, a novel manufacturing facility should be introduced, which could disadvantageously increase redemption for the installation. In an absorbent heat cycle test, peeling might arise.
SUMMARY OF THE INVENTION
The present invention is directed to a solution to the above-described problem, and it is an object of the present invention to provide a resin-encapsulated semiconductor device comprising a resin integrally encapsulating a plurality of semiconductor chips including at least one center pad type semiconductor chip, so that the integration capacity can be increased, the function can be improved and a thin, compact, inexpensive and reliable package can be obtained.
According to present invention, A resin-encapsulated semiconductor device, comprising:
a first semiconductor chip provided with a plurality of electrodes on a centerline at the center of an upper surface thereof,
first metal wires each connected to each electrode of the first semiconductor chip,
a second semiconductor chip provided with a plurality of electrodes at an end of an upper surface thereof,
second wires each connected to each electrode of the second semiconductor chip,
a die pad having at least one die bond surface, and supporting the first and second semiconductor chips, and
a plurality of inner leads arranged near an end of the die pad, wherein
the plurality of inner leads each having a first surface to which each of the first metal wires is wire-bonded, and a second surface to which each of the second metal wires is wire-bonded, and
the first and second surfaces being positioned on different planes substantially parallel to the die bond surface and apart from one another.
By the structure of the resin-encapsulated semiconductor device, a compact and thin resin-encapsulated semiconductor device with large capacity which has two semiconductor chips stored therein and allows the metal thin lines from contacting the edge of the chips. In the arrangement in which the first and second surfaces are positioned on different planes substantially parallel to the die bond surface and apart from one another, at least one semiconductor chip has a plurality of electrodes on a centerline thereof, and if a metal wire connecting an electrode thereof and an inner lead is long, the metal thin line can be effectively prevented from contacting the edge of the semiconductor chip.
And a resin-encapsulated semiconductor device according to the present invention, comprising:
a die pad having first and second die bond surfaces opposing each other,
a first semiconductor chip die-bonded on the first die bond surface having a plurality of electrodes on a centerline at the center of an upper surface thereof,
first metal wires each connected to each electrode of the first semiconductor chip,
a second semiconductor chip die-bonded on the second die bond surface having a plurality of electrodes on a centerline at the center of an upper surface thereof,
second wires each connected to each electrode of the second semiconductor chip, and
a plurality of inner leads arranged near an end of the die pad, wherein
the plurality of inner leads each having a first surface to which each of the first metal wires is wire-bonded, and a second surface to which each of the second metal wires is wire-bonded, and
the first and second surfaces being positioned on different planes substantially parallel to the die bond surface and apart from one another.
Also a resin-encapsulated semiconductor device according to the present invention, comprising:
a die pad having two opposing die bond surfaces,
two semiconductor chips each die-bonded to each of the die bond surfaces, and having a thickness of at most 150 &mgr;m provided with elec

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