Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-11-05
2002-12-17
Lee, Eddie (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S780000
Reexamination Certificate
active
06495916
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating same, and more particularly, to a semiconductor device which is resin-encapsulated in a semiconductor wafer state and a method of fabricating the semiconductor device. Thus, the invention deals with such a semiconductor device as described above having high reliability for interconnection and a method of fabricating the semiconductor device.
2. Description of the Related Art
Portable equipment have lately come into widespread use at a rapid pace, and this has been accompanied by increasing demands calling for semiconductor devices mounted therein that are thinner in thickness, smaller in size, and lighter in weight than conventional ones. Thereupon, a number of packaging technologies have been proposed in order to cope with such demands.
As one of such technologies, a chip size package (referred to hereinafter as CSP) equivalent or substantially equivalent in size to a semiconductor chip with an integrated circuit formed thereon has been developed.
There has been available a conventional CSP wherein a rewiring made of Cu, to be connected to each of electrode pads of a semiconductor chip, is formed, a terminal called a post, to be connected to the rewiring, is formed for redisposing the electrode pads, the surface of the semiconductor chip is encapsulated with resin to a height of the terminals, and a metallic electrode such as a solder ball etc. is provided at the tip of the respective terminals, exposed out of the resin.
In a method of fabricating the CSP, a polyimide layer is first formed over a semiconductor wafer, a rewiring pattern made of Cu, to be connected to an electrode pad of a plurality of semiconductor chips formed on the semiconductor wafer, is formed, and a terminal called a post, to be connected to respective rewirings, is formed, thereby redisposing the electrode pads. Subsequently, the entire surface of the semiconductor wafer with the terminals formed thereon is resin-encapsulated, and after curing of resin the resin is abraded to the extent that the tip of the respective terminals is exposed. And the exposed tip of the respective terminals is provided with a metallic electrode such as a solder ball etc. before dicing the semiconductor wafer into separated pieces for individual semiconductor chips.
However, when a temperature cycle test is repeatedly conducted on such a CSP as described above after it is mounted on a substrate, there arises a possibility of cracks occurring to the metallic electrodes such as the solder balls etc. This is attributable to a large difference in thermal expansivity between the CSP and the substrate, and also to a small area of bonding between the respective metallic electrodes and the respective terminals of the CSP due to a narrow spacing between the terminals.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor device having high reliability for interconnection and a method of fabricating the semiconductor device. To this end, the invention provides a semiconductor device comprising a semiconductor chip having a plurality of electrode pads formed on the upper surface thereof, a terminal formed on the upper surface of the semiconductor chip, electrically connected to each of the electrode pads, and a resin formed on the upper surface of the semiconductor chip, encapsulating the terminals such that the terminals are exposed out of the resin to the extent of a predetermined height. Further, the present invention provides a method of fabricating the semiconductor device comprising a step of forming a terminal on a plurality of chips formed on a semiconductor wafer, respectively, said terminal being electrically connected to an electrode pad of the respective chips, a step of forming a resin on the upper surface of the semiconductor wafer, on the side of the terminals, so as to encapsulate the terminals, a step of abrading the resin to the extent that the respective terminals is exposed out of the resin, a step of exposing the side wall face of the respective terminals by removing a portion of the resin, around the respective terminals, and a step of dicing the semiconductor wafer into separated pieces for the respective chips.
REFERENCES:
patent: 5467253 (1995-11-01), Heckman et al.
patent: 5591941 (1997-01-01), Acocella et al.
patent: 5656550 (1997-08-01), Tsuji et al.
patent: 5872399 (1999-02-01), Lee
patent: 6024584 (2000-02-01), Lemke et al.
patent: 10-050772 (1998-02-01), None
Net's Report; Nikkei Electronics; Japan; Published Mar. 8, 1999; No. 738, pp. 174-175; Partial Translation provided, total 5 pages.
“A Candidate for the Chip Size Mounting and a Cheap Method for Producing CSPs Emerges Packages Created in the Wafer Level Process”; Toshimi Kawahara/Development Department; Nikkei Microdevices; Japan; Published Apr. 1998; pp. 164 -167, total 9 pages.
“Connection Reliability Requirements, Cleared by CSPs That Underwent Structural Modifications”; Nikkei Microdevices; Published Feb. 1998; pp. 48 -53; Partial Translation provided, total 15 pages.
Kobayashi Harufumi
Ohuchi Shinji
Shiraishi Yasushi
Lee Eddie
Pizarro-Crespo Marcos D.
Rabin & Berdo P.C.
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