Resin-encapsulated LOC semiconductor device having a thin inner

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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Details

257668, 257691, H01L 2348, H01L 23495, H01L 2352

Patent

active

060465042

ABSTRACT:
A semiconductor device of the present invention has an LOC (Lead On Chip) structure. An end portion of an inner lead made thinner than an outer lead by cutting its lower surface by a predetermined thickness and a bus bar thinned to have the same thickness as the end portion of the inner lead are bonded to the surface of a semiconductor chip on which circuits are formed, with a protective film and an insulating tape interposed therebetween. A bonding wire is bonded to the thin portion of the inner lead or the thin bus bar. The thickness from the upper surface of the semiconductor chip to the upper surface of the inner lead can be reduced by the cut portion. A thin package can be realized without deteriorating the reliability with the normal thickness of the outer lead, the insulating tape and an encapsulating resin and the normal loop height of the bonding wire.

REFERENCES:
patent: 4810620 (1989-03-01), Takiar et al.
patent: 5796158 (1998-08-01), King
patent: 5834831 (1998-11-01), Kubota et al.
patent: 5859471 (1999-01-01), Kuraishi et al.

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