Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
1996-10-21
2001-02-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C361S776000
Reexamination Certificate
active
06184587
ABSTRACT:
Heretofore many types of interconnections which have been provided for use with the semiconductor devices have suffered from one or more disadvantages limiting their broad application in the semiconductor industry. There is therefore need for new and improved interconnection contact structure which overcomes such disadvantages so that it will be particularly useful in semiconductor assemblies and packages and which can be broadly used throughout the semiconductor industry.
In general, it is an object of the present invention to provide a contact structure, interposer, a semiconductor assembly and package using the same and a method for fabricating the same which makes it possible to use contact structures and particularly resilient contact structures attached directly to active silicon devices.
Another object of the invention is to provide a structure, interposer, assembly and method of the above character which makes it possible to make temporary contacts against pads for burn-ins on test substrates.
Another object of the invention is to provide a structure, interposer, assembly and method of the above character which makes it possible to utilize spacings or pitches at the originating points for the contact structures which are different from the terminating points for the contact structure.
Another object of the invention is to provide a structure, interposer, assembly and method which utilizes staggered contact structures making possible three-dimensional fanouts.
Another object of the invention is to provide a structure, interposer, assembly and method of the above character which make it possible for the contact structures to be attached to pads in area arrays, peripheral, edge or center line pad outs.
Another object of the invention is to provide a structure, interposer, assembly and method of the above character which with one sided edge pad outs, the contact can be shaped in a way that enables closely spaced edge mounting of chips on SIMM and other cards.
Another object of the invention is to provide a structure, interposer, assembly and method of the above character which makes it possible to mount contacts on devices in either wafer or singulated form.
Another object of the invention is to provide a structure, interposer, assembly and method in which contact attachment can be accomplished with automatic equipment.
Another object of the invention is to provide a structure, interposer, assembly and method which makes it possible to utilize under chip capacitors to save in real estate.
Another object of the invention is to provide a structure, interposer, assembly and method of the above character which can be utilized for providing more than one substrate precursor populated with card ready silicon on both sides which optionally can be interconnected with resilient contacts.
REFERENCES:
patent: 3087239 (1963-04-01), Clagett
patent: 3519890 (1970-07-01), Ashby
patent: 3747198 (1973-07-01), Benson et al.
patent: 3787966 (1974-01-01), Klessika
patent: 3842189 (1974-10-01), Southgate
patent: 4385341 (1983-05-01), Main
patent: 4618879 (1986-10-01), Mizukoshi et al.
patent: 4728751 (1988-03-01), Canestare
patent: 4764848 (1988-08-01), Simpson
patent: 4893172 (1990-01-01), Matsumoto et al.
patent: 4996629 (1991-02-01), Christiansen et al.
patent: 5091772 (1992-02-01), Kohara et al.
patent: 5166774 (1992-11-01), Banerji et al.
patent: 5296744 (1994-03-01), Liang et al.
patent: 5317479 (1994-05-01), PAi et al.
patent: 5349495 (1994-09-01), Visel et al.
patent: 5359227 (1994-10-01), Liang et al.
patent: 5389743 (1995-02-01), Simila et al.
patent: 5396104 (1995-03-01), Kimura
patent: 5476211 (1995-12-01), Khandros
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5536973 (1996-07-01), Yamaji
patent: 5606196 (1997-02-01), Lee et al.
patent: 5639558 (1997-06-01), Tatsumi et al.
patent: 5656830 (1997-08-01), Zelhman
patent: 0 528 367 (1993-02-01), None
patent: 0 593 966 (1994-04-01), None
patent: 2 643 753 (1990-08-01), None
patent: 61 287254 (1986-12-01), None
Chip Column Package Structure, IBM Tech. Discl. Bull. vol. 40 No. 08 pp. 117-118, Aug. 1997.
“Method of Testing Chips and Joining Chips to Substrates” Research Disclosure, No. 322, Feb. 1, 1991, p. 130, XP000169195.
“Bimetal VLSI Chip Interconnections” IBM Technical Disclosure Bulletin, vol. 29, No. 11, Apr. 1987, pp. 5021-5022, XP002040446.
Khandros Igor Y.
Mathieu Gaetar L.
Chaudhuri Olik
FormFactor Inc.
Kelley Nat
Larwood David
Linden Gerald
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