Residue number system shift accumulator decoder

Details Residue number system shift accumulator decoder Residue number system shift accumulator decoder

1987-02-02

1989-03-28

Shoop, Jr., William M.

Coded data generation or conversion

Digital code to digital code converters

To or from mixed base codes

364746, 36472401, H03M 700

Patent

active

048168050

ABSTRACT:
Signal processing techniques are disclosed for applications such as finite impulse response filtering. After initial processing in residue number system (RNS) channels, the signals are converted from residue form to a true external representation of the filter output. The conversion employs a chinese remainder theorem decoder and shift accumulator controlled to utilize adaptive modulo reduction. As a consequence, each modulus function value is reduced during computation when it exceeds the modulus and not at the end of the function evaluation. This reduces hardware requirements by minimizing the arithmetic word length. In implementing the technique, each function value is tested to see if it is within a modulus range and the corresponding modulus value is subtracted if it is not. This is done as many times as is necessary to bring each function value within the range. By utilizing this technique, speed and computational accuracy are improved in filter processes thereby producing improved performance in radar, seismic, acoustic and other applications which depend on such filter characteristics.

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Jenkins, W. and Leon, B., "The Use of Residue Number Systems in the Design of Finite Impulse Response Digital Filters", pp. 196-197 (1977).
Szabo, N. and Tanaka, R., Residue Arithmetic and its Applications to Computer Technology, chapters 1 and 2 attached, pp. 27-32 (1967).
Taylor, F., "Large Moduli Multipliers for Signal Processors", (1981).
Vojir, W. "Hardware Design for New Digital Signal Processing Techniques", (1980).

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