Residue generators for reduction of charge injection in...

Details Residue generators for reduction of charge injection in... Residue generators for reduction of charge injection in...

2008-11-05

2010-06-01

Nguyen, Linh V (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S118000, C341S120000, C341S155000, C341S162000, C341S172000

Reexamination Certificate

active

07728752

ABSTRACT:
Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.

REFERENCES:
patent: 5180932 (1993-01-01), Bengel
patent: 5574457 (1996-11-01), Garrity et al.
patent: 5923206 (1999-07-01), Levinson
patent: 6172629 (2001-01-01), Fetterman
patent: 6545628 (2003-04-01), Aram
patent: 6559787 (2003-05-01), Aude et al.
patent: 6600440 (2003-07-01), Sakurai
patent: 6756929 (2004-06-01), Ali
patent: 6801151 (2004-10-01), Opris
patent: 6954169 (2005-10-01), Min
patent: 6967611 (2005-11-01), Atriss et al.
patent: 6970038 (2005-11-01), Chandrasekaran
patent: 7002505 (2006-02-01), Hughes
patent: 7009549 (2006-03-01), Corsi
patent: 7068203 (2006-06-01), Maloberti et al.
patent: 7106240 (2006-09-01), Cringean
patent: 7339512 (2008-03-01), Gulati et al.
patent: 7414564 (2008-08-01), Ali
patent: 7612700 (2009-11-01), Kawahito et al.
patent: 7623051 (2009-11-01), Murden et al.
patent: 7633423 (2009-12-01), Cho
Chiu, Yun, et al., “A 14-b 12-MS/s CMOS Pipeline ADC with over 100-dB SFDR”, IEEE Journal of Solid-State Circuits, vol. 39, No. 12, Dec. 2004, pp. 2139-2151.
Sonkusale, Sameer, Background Digital Error Correction Technique for Pipelined Analog-Digital Converters, 2001 IEEE, Sep. 2001, pp. I-408 to I-411.

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