Residue-compensating A/D converter

Details Residue-compensating A/D converter Residue-compensating A/D converter

2001-03-05

2003-04-29

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

C341S156000

Reexamination Certificate

active

06556158

ABSTRACT:

1. FIELD OF INVENTION
The field of invention is data conversion, more particularly, this invention relates to multi-step analog-to-digital converters.
1.2 Inventor
Jesper Steensgaard-Madsen, 448 Riverside Drive, apartment # 2, New York, N.Y. 10027, USA, is the sole inventor and applicant. The applicant is a citizen of Denmark.
2. DESCRIPTION OF PRIOR ART
Highly-linear high-speed analog-to-digital converters (ADCs) are key elements in many electrical systems of great importance. Digital communication systems, e.g., digital-subscriber-line (xDSL) modems, which are capable of providing wide-bandwidth communication via traditional phone lines, are an example of where a system's overall performance may be limited by the ADC front-end's finite linearity. The available high-performance ADCs needed for xDSL modems are relatively expensive and will often represent a large fraction of the system's overall cost. Furthermore, considering that the required good linearity usually is achieved by brute-force calibration of the ADC circuit, the long-term performance reliability may be poor due to aging, ambient temperature variations, and other effects which may cause the circuit's electrical properties to drift.
2.1 Multi-Step A/D Converters
Multi-step conversion techniques are generally preferred for the implementation of wide-bandwidth high-resolution ADCs. Pipelined multi-step ADCs, hereinafter simply called pipeline ADCs, are generally implemented using switched-capacitor (SC) circuit techniques and may be used for applications with a sampling rate of up to 100 MHz (sometimes even more). Pipeline ADCs' market share is significant due to the relatively good linearity and bandwidth achievable at a low cost and circuit complexity.
FIG. 1
shows a typical 5-step pipeline ADC [
50
]. The input signal g(t) is sampled at equidistant instances in time (the symbol g(k) represents g(t) for t=k. T
clk
, where k is integer and T
clk
is the sampling period) and converted into a first coarse (having, say, 3 bits of resolution) digital representation d
0
(k) by a first flash quantizer [
52
]. The residue r
0
(k) of g(k) with respect to d
0
(k)·K
0
, where K
0
is the reciprocal of the ADC's [
50
] gain, is calculated by the first residue stage [
54
]. In the ideal case, the following relationship will result: g(k)=d
0
(k)·K
0
+r
0
(k). The objective is to generate an estimate d
r0
(k) of r
0
(k)/K
0
, whereby an estimate d
0
(k) of g(k)/K
0
can be easily calculated: d
g
(k)=d
0
(k)+d
r0
(k). In other words, d
r0
(k) compensates for the residue r
0
(k) of the first-stage quantization d
0
(k), i.e., the system [
50
] is a multi-step residue-compensating ADC.
Gain Scaling.
An amplified version A
0A
·r
0
(k), rather than r
0
(k) itself, is quantized to A
0D
·d
r0
(k), where nominally A
0A
=A
0D
=A
0
. The analog-domain amplification, A
0A
, can easily be made an integral part of the residue stage [
54
] (discussed below). The advantage of amplifying the analog signal level by A
0
is that noise, offset, and all other errors from the residue quantizer [
58
], will be suppressed by 1/A
0
when referred to the output signal d
g
(k). It is thus preferable to make A
0
large. How large A
0
can be made depends on the magnitude of r
0
(k) relative to the residue quantizer's [
58
] full-scale range, i.e., A
0
will largely be proportional to the resolution of d
0
(k).
Digital Correction.
FIG. 2
shows an example of a typical nominal characteristic of 4 r
0
(k) as a function of g(k) when using a 5-level flash quantizer [
52
]. It is assumed that the overall pipeline ADC [
50
D], as well as the residue quantizer [
58
], is able to resolve their respective input signals in a range from −V
ref
to +V
ref
. Notice that the chosen gain factor A
0
=4, in principle, can be increased from 4 to 5. However, choosing A
0
as the nominally largest possible value is not recommendable because the flash quantizer [
52
] will generally be subject to substantial imperfections
onlinearities, in which case the amplified residue signal 4·r
0
(k) rather will be described by the qualitative characteristic shown in FIG.
3
. It is a key point that the overall operation will be robust with respect to all errors from the flash quantizer [
52
], provided that A
0
·r
0
(k) is calculated correctly and the residue quantizer [
58
] is not overloaded. The concept of deliberately under designing the residue stage's [
54
] gain factor, A
0
, is usually called for “digital correction.” Because it is a very simple and low-cost way to avoid potentially large nonlinearities due to displacement of the flash quantizer's [
52
] threshold voltages, digital correction is used extensively in essentially all modern pipeline ADCs.
Pipelining.
Consider again FIG.
1
. From a simplistic point of view (i.e., when neglecting the impact of digital correction), d
0
(k) is the most significant digit and d
r0
(k) the least significant digits of d
g
(k) represented in a number system which is not necessarily the Arabian base-10 system. Thus, a pipeline ADC [
50
] may be construed as a system that digitizes the input signal g(k) sequentially one digit at a time (here, for simplicity, assuming that all signals have the same resolution, which need not be the case): d
0
(k), d
1
(k), d
2
(k), d
3
(k), and then d
4
(k). To allow a high sampling rate, the determination of the individual digits is spread over several clock cycles and separate circuit stages. In other words, the first stage [
56
] determines the most-significant digit of the most recent sample of g(k), while the residue quantizer [
58
] determines the less-significant digits in the four previous samples (one digit per input sample per clock cycle). It is, therefore, necessary to delay individually the digit signals, d
0
(k), d
1
(k), d
2
(k), d
3
(k), and d
4
(k), such that the digits representing the same input sample are combined to form one sample of d
g
(k). The technique of staggering in time and spreading over several circuit stages the determination of the individual digits is called “pipelining.”
Implementation.
FIG. 4
shows a simplified representation of the pipeline ADC [
50
] from
FIG. 1
; the simplification lies only in the more compact representation of the residue quantizer [
58
]. This simplified representation is particularly useful if the gain factor A
0
is relatively high, in which case the subsequent quantizer [
58
] often can be modeled by an ideal one when evaluating the overall performance. In fact, the residue quantizer [
58
] is often designed using second-grade circuitry with low power consumption, such that its linearity is only as good as necessary. Assuming that this assumption is justifiable, and that digital correction is used wisely, it may be concluded that the errors that will limit the ADC's [
50
] performance will originate from imperfections in the first residue stage [
54
].
FIG. 5
shows how the input stage [
56
] can be implemented efficiently. The flash quantizer [
52
] is based on an array of latches [
60
] (for simplicity, only four latches [
60
] are shown, although the use of 8, 16, or even 32 latches generally is preferable) and a resistor ladder [
62
] generating the latches' [
60
] nominal threshold voltages. Four boolean signals, x
0
, x
1
, x
2
, and x
3
, generated when strobing the latches [
60
] represent d
0
(k) in a so-called thermometer code.
The DAC is implemented by a voltage buffer [
64
], buffering each of the four boolean signals to plus/minus the reference voltage (±V
ref
), and an array of nominally identical capacitors [
66
]. The DAC capacitors [
66
] and the gain-scal

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