Residual status reporting during chained cycle steal input/outpu

Details Residual status reporting during chained cycle steal input/outpu Residual status reporting during chained cycle steal input/outpu

1976-04-30

1977-10-11

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 300

Patent

active

040539504

ABSTRACT:
A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.

REFERENCES:
patent: 3487370 (1969-12-01), Goshorn et al.
patent: 3728693 (1973-04-01), Macker et al.
patent: 3938101 (1976-02-01), Lewis et al.

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