Residual charge elimination for a memory device

Details Residual charge elimination for a memory device Residual charge elimination for a memory device

1995-12-29

1998-03-31

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36523006, G11C 1134

Patent

active

057346089

ABSTRACT:
A circuit and method is provided for addressing memory cells in a memory device, including two series connected select gates having a node between them. A switching element is connected between the node and a ground voltage. A control signal is applied to a control input of the switching element to render it conductive while both of the select gates are non-conductive, so as to eliminate charge stored at a node between the two select gates. A particular application to an addressing circuit for use in a flash EPROM memory device is described.

REFERENCES:
patent: 5016216 (1991-05-01), Ali
patent: 5491658 (1996-02-01), Schreck
patent: 5511032 (1996-04-01), Kammerev
patent: 5602796 (1997-02-01), Sugio
"High Density Memory Selection Circuit," IBM Technical Disclosure Bulletin 15, (7): 2042-2044, Dec. 1972.

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