Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2004-03-30
2011-12-20
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
08082419
ABSTRACT:
According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results.
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patent: 2002/0065860 (2002-05-01), Grisenthwaite et al.
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patent: 2004/0034760 (2004-02-01), Paver et al.
Aldrich Bradley C.
Ganeshan Murli
Paver Nigel C.
Blakely , Sokoloff, Taylor & Zafman LLP
Chan Eddie P
Intel Corporation
Lindlof John
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