Resetting system

Details Resetting system Resetting system

1985-03-04

1989-02-07

Shaw, Gareth D.

Excavating

371 62, 364200, G06F 1100

Patent

active

048036820

ABSTRACT:
A resetting system including a main CPU for an apparatus, and a slave CPU for controlling a terminal portion of the apparatus in association with a watch-dog timer, wherein the main CPU outputs for a predetermined period of time a strobe signal to be supplied to the watch-dog timer, which outputs a reset signal for resetting both the main CPU and slave CPU when the periodical supplying of strobe signals is stopped, indicating an abnormal state of the main CPU. The slave CPU sends a response data corresponding to a command from the main CPU, whereby the main CPU judges as a communication error a response data not in conformity with a predetermined format and, upon the generation of a number of communication errors in succession, the slave CPU is reset by a reset signal outputted from the main CPU.

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