Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-05-14
2001-08-07
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S211000, C327S225000, C326S093000
Reexamination Certificate
active
06271701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to flip-flop structures.
2. Description of the Related Art
The output of a simple latch (sometimes referred to as an unclocked latch) is continuously responsive to its data inputs. Level-sensitive latches (sometimes referred to as gated latches) also have an enable input (which may be a clock pulse) and these latches continuously sample their inputs while they are enabled. During the enable time period, any input change immediately appears at the latch output. When the enable signal terminates, the last value of the input determines the state held, i.e., “latched”, at the latch output.
In contrast, the outputs of flip-flops never have an enable time period in which input state changes are transparently received at the output but, rather, the outputs change to the input states at a clock transition (e.g., the clock's positive edge or the clock's negative edge).
The output signal of a D flip-flop takes on the state of a DATA signal in response to each clock pulse of a clock (CLK) signal. Accordingly, its output signal may be in error because it does not fully respond to events that occur in the DATA signal. The sources of these errors is demonstrated in
FIGS. 1 and 2
which respectively show an exemplary D flip-flop
20
and a timing diagram
60
that illustrates waveforms in the flip-flop
20
.
In particular, the flip-flop
20
is formed of a series connection of two D latches—a master latch
22
and a slave latch
24
. When a CLK signal at a CLK input
26
is in its low state, the master latch
22
receives DATA signals from a DATA input
28
at the S input of an R-S latch
30
and receives an inverted version of the DATA signals at an R input of the R-S latch. The inverted version is formed by an inverter
34
.
These inputs reach the R-S latch during the low CLK signal because the CLK input
26
is coupled through an inverter
39
to one input of each of a pair of AND gates
36
and
38
and they are respectively connected to the S and R inputs of the R-S latch
30
and because DATA signals at the DATA input
28
and an inverted version of the DATA signals are respectively connected to other inputs of the AND gates
36
and
38
.
The structure of the master latch
22
causes a path
40
to be “transparent” during low portions (the enable state) of a CLK signal at the CLK input
26
and to be latched during high portions of the CLK signal. Thus, DATA signals at the DATA input
28
appear at the Q output
42
of the R-S latch
30
during low CLK portions and are held at this output during high CLK portions.
The slave latch
24
is identical to the master latch
22
with like elements indicated by like reference numbers. However, the AND gates
36
and
38
of this latch receive the CLK signal directly and, accordingly, the slave latch
24
has a path
50
that is “transparent” during high portions of the CLK signal at the CLK input
26
and that is latched during low portions of the CLK signal.
The flip-flop
20
is typically referred to as a pulse-triggered or master-slave flip-flop.
FIG. 1
shows an exemplary realization but many others (e.g., with OR gates) are well known. Operation of master-slave flip-flops is described in a variety of references (e.g., Floyd, Thomas L.,
Digital Fundamentals,
Macmillan Publishing Company, 1994, New York, pp. 381, 382 and 389-392 and Katz, Randy H.,
Contemporary Logic Design,
Benjamin/Cummings Publishing Company, 1994, Redwood City, Calif., pp. 381, 382 and 389-392).
In particular, operation of the flip-flop
20
is illustrated in
FIG. 2
which applies a CLK signal
62
and an exemplary DATA waveform
64
to the CLK input
26
and DATA input
28
. In response, a MASTER OUTPUT signal
66
appears at the Q output
42
of the master latch
22
. Note that the signal
66
is identical to the DATA signal
64
when the CLK signal
62
is low (because the path
40
is “transparent” at this time) but is latched at the leading edges
68
of clock pulses
70
. Accordingly, it differs from the DATA signal in waveform portions
72
and
74
of that signal.
In response to the MASTER OUTPUT signal
66
, a SLAVE OUTPUT signal
76
appears at the Q output
52
of the flip-flop
20
. This signal is identical to the latched MASTER OUTPUT signal
66
when the CLK signal
62
is high (because the path
50
is “transparent” at this time) but is itself latched at trailing edges
78
of the CLK signal
62
.
The output signal at the Q output
52
of the flip-flop
20
thus tracks the DATA signal
64
at leading edges
68
of the clock pulses
70
but, as seen in
FIG. 2
, this output signal can change state only at the leading edges
68
. To see why this may introduce errors in the output signal, let it be assumed that the high portions
80
,
82
,
84
and
86
of the DATA signal
64
represent “events” (e.g., output signals of a device under test) and that it is wished to monitor these events with the flip-flop
20
.
In this application, the flip-flop
20
preferably senses the events and reflects that in the SLAVE OUTPUT
76
at the Q output
52
. As shown in
FIG. 2
, however, the SLAVE OUTPUT signal
76
has high portions
90
and
92
that indicate the presence of events
80
and
84
but fails to indicate the presence of events
82
and
86
. The use of the flip-flop
20
is therefore limited to applications of event monitoring in which events occur at a rate less than (½)f
CLK
wherein f
CLK
is the clock rate.
Trigger generation is another application in which the flip-flop
20
has limited use. It may be desired, for example, to generate a sequence of trigger pulses when the DATA signal is high and cease generation when it is low. Although the flip-flop
20
can generate such a sequence, the trigger rate is limited to (½)f
CLK
because the output of the flip-flop
20
can only change state at each clock pulse's leading edge.
SUMMARY OF THE INVENTION
The present invention is directed to flip-flops that can monitor events and generate sequences of trigger pulses at high rates. In contrast to conventional flip-flops, they reset between clock pulses and, accordingly, they can monitor events that occur as rapidly as the clock rate and can generate trigger pulses at the clock rate.
A flip-flop embodiment of the invention includes a latch and an AND gate wherein the latch has a data input port for reception of a data signal and a clock input port for reception of a clock signal and further has a latch output port for presentation of a latched output signal whose state during each clock pulse is that of the data signal at that pulse's leading edge. When first and second gate input ports are respectively coupled to the latch output port and the clock input port, the flip-flop's output signal is delivered at the gate's output port and, accordingly, the output signal is reset to a selected logic value between clock pulses.
In a method of the invention, a sequence of trigger pulses is generated from a digital data signal and a clock signal of clock pulses that each have a leading edge. The method has a first process in which a leading-edge logic value of the data signal is sensed at each leading edge. For the duration of each clock pulse, the logic value of the data signal is then replaced with the respective leading-edge logic value to thereby form a latched data signal. In a third process step, the latched data signal and the clock signal are anded to generate an output signal. Finally, sequences of trigger pulses are gated into the output signal by alternating the data signal between first and second logic values.
The teachings of the invention can be practiced with various logic circuit structures, e.g., emitter-coupled logic (ECL).
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5017814 (1991-05-01), Lloyd
patent: 5254888 (1993-1
Analog Devices Inc.
Callahan Timothy P.
Koppel & Jacobs
Luu An T.
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