Reset voltage generation circuit for CMOS imagers

Details Reset voltage generation circuit for CMOS imagers Reset voltage generation circuit for CMOS imagers

2005-12-06

2005-12-06

Pyo, Kevin (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C348S308000

Reexamination Certificate

active

06972399

ABSTRACT:
A reset voltage generator for CMOS imagers is disclosed. The voltage generator contains a “top” voltage generator and a “bottom” voltage generator, both of which are switched in and out of operation. A predetermined reset voltage is thereby generated independent of the power supply voltage (e.g., Vdd) and independent of any noise and/or voltage shifts associated with the power supply voltage.

REFERENCES:
patent: 2003/0133030 (2003-07-01), Borg

Affiliated with

Also associated with

Rating

Reset voltage generation circuit for CMOS imagers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reset voltage generation circuit for CMOS imagers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reset voltage generation circuit for CMOS imagers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3504304