Reset signal generation circuit

Details Reset signal generation circuit Reset signal generation circuit

1999-09-08

2001-06-26

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000

Reexamination Certificate

active

06252444

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock signal generation circuit in a semiconductor chip and more particularly to a reset signal generation circuit for generating internal clock signals in a chip.
2. Description of Related Art
It takes a little time for a stable clock signal to be generated after a chip is powered and an oscillation circuit is activated. This period of time is called an oscillation-stability time. During the oscillation-stability time, reset signals are generated not to let the chip operate. Because not only power supply voltage is not sufficiently ensured, but also frequency of a clock signal is not stabilized during the oscillation-stability time, stability of circuit operation cannot be guaranteed, so the chip is prevented from operating using the reset signal.
FIG. 1
is a block diagram of a related art reset signal generation circuit.
Oscillator
102
performs oscillating operation in response to an incoming external clock signal, CLK_EXT.
Clock generator
104
receives an oscillation signal from the oscillator
102
and an external reset signal, /RST_EXT, and generates an internal clock signal, CLK_INT, of a predetermined frequency. The external reset signal, /RST_EXT, has an initial value of a low level and is provided as an internal reset signal, /RST_INT, to prevent the remaining elements other than the clock generator
104
from being activated.
FIG. 2
is a timing chart for showing an operating characteristic of the above related art reset signal generation circuit.
Once the chip is powered and a level of power voltage, VCC, starts to increase, oscillation of the internal clock signal, CLK_INT, starts. The frequency of the internal clock signal, CLK_INT, is not stable because the level of the power voltage, VCC, is not sufficient. At this time, the internal reset signal, /RST_INT, has a low level, so other elements in the chip do not operate.
Once the power voltage level is sufficiently ensured during the oscillation-stability time and the oscillation-stability time has been passed, the internal reset signal, /RST_INT, goes to a high level. Since the frequency of the internal clock signal, CLK_INT, is satisfactorily stable at this time, the chip becomes to operate in normal.
However, the related art reset signal generation circuit should detect a settling time of the oscillator in advance and ensure a corresponding oscillation-stability time. Such fixed oscillation-stability time may delay the start of operation of the chip unnecessarily or may not ensure an enough oscillation-stability time because the circuit cannot reflect the condition when the operating characteristic of the oscillator deteriorates.
Moreover, since the operating characteristic of the oscillator generating the oscillation signal using the external clock signal, CLK_EXT, depends upon the external clock signal, CLK_EXT, a characteristic of the oscillation signal generated by the oscillator
102
is also unstable if the external clock signal, CLK_EXT, becomes unstable.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a reset signal generation circuit that substantially obviates one or more of the limitations and disadvantages of the related art.
An objective of the present invention is to provide a reset signal generation circuit for generating a reset signal according to a state of an external clock signal and states of output signals of phase locked loops (PLLs) to optimize a generation time point of the reset signal.
Additional features and advantages of the invention will be set forth in the following description, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure as illustrated in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a reset signal generation circuit of the present invention comprises a phase locked loop (PLL) selector, a plurality of PLLs, a locking detector, a clock selector, a counter, and a reset synchronizer.
The PLL selector is activated when an external reset signal is high and selectively provides one of a power down control signal and an external clock signal.
The plurality of PLLs have different input frequency signals and different output frequency signals. They are activated in response to an external clock signal and inactivated in response to the power down control signal.
The locking detector detects locking/unlocking of the PLLs based upon the output frequency signals of the PLLs and generates a locking signal.
The clock selector selects one of the output signals of the PLLs and the external clock signal and provides the selected signal as an internal clock signal.
The counter counts the predetermined number of internal clock signals and generates an overflow signal after completing the count.
In response to the overflow signal of the counter, the reset synchronizer generates an internal reset signal synchronizing with the locking signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5671260 (1997-09-01), Yamauchi et al.
patent: 5786717 (1998-07-01), Yu

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