Reset signal filter

Details Reset signal filter Reset signal filter

2008-12-24

2010-06-29

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S198000, C327S551000

Reexamination Certificate

active

07746131

ABSTRACT:
A reset signal filter includes a power voltage detector and a reset signal detector or includes only one reset signal detector. The power voltage detector includes a comparators and a basic logic gates (e.g. AND gate, OR gate, inverter, etc). The reset signal detector includes a comparator, N flip flops connected in series, an AND gate, an OR gate, a multiplexer and an output flip flop. The reset signal filter receives a first reset signal generated by a power voltage detector or a Schmitt trigger buffer and utilizes N flip flops to register the signal level of the first reset signal for N clock periods. Then the reset signal filter determines if the first rest signal is changed during N clock periods, and outputs a second reset signal.

REFERENCES:
patent: 6175603 (2001-01-01), Chapman et al.
patent: 6252466 (2001-06-01), Kawamura
patent: 6823029 (2004-11-01), Chapman et al.

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