Reset generation circuit to reset self resetting CMOS circuits

Details Reset generation circuit to reset self resetting CMOS circuits Reset generation circuit to reset self resetting CMOS circuits

1994-11-21

1995-11-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327143, 327198, 326 94, 377 73, 377 78, H03L 700

Patent

active

054670373

ABSTRACT:
A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

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T. Chappell et al.; "A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture"; IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1577-1585.

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