Reset feature for a low voltage differential latch

Details Reset feature for a low voltage differential latch Reset feature for a low voltage differential latch

2002-11-25

2004-09-28

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S217000, C327S218000

Reexamination Certificate

active

06798263

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to differential digital latch circuits. More particularly, the present invention relates to a reset function for a differential latch operating at a low voltage.
BACKGROUND OF THE INVENTION
High speed digital data communication systems may utilize fully differential latches to process data Differential latches are commonly used because they reduce the effects of coupling noise.
FIG. 1
is a schematic representation of a prior art differential latch circuit
100
having a differential reset feature. The input data signal
102
, the clock signal
104
, the reset signal
106
, and the output data signal
108
are differential, which forces the structure of circuit
100
to have four active devices (e.g., transistors) connected in series. In this regard, a first transistor level accommodates input data signal
102
, a second transistor level accommodates clock signal
104
, a third transistor level accommodates reset signal
106
, and a fourth transistor level functions as a bias current source for latch circuit
100
.
The reset operation of latch circuit
100
is performed when reset signal
106
corresponds to a logic high value. When reset signal
106
is high, transistor M
8
is switched on and transistor M
7
is switched off. Under these conditions, transistor M
8
steers the bias current (generated by transistor M
9
) away from transistors M
1
-M
6
, thus switching transistors M
1
-M
6
off. In this state, the positive component of output data signal
108
becomes VDD minus the voltage drop across resistance R, and the negative component of output data signal
108
becomes VDD, resulting in a logic low value for output data signal
108
.
The normal operation of latch circuit
100
is performed when reset signal
106
corresponds to a logic low value. When reset signal
106
is low, transistor M
8
is switched off and transistor M
7
is switched on. Under these conditions, transistor M
7
steers the bias current to transistors M
1
-M
6
, which perform a conventional latching function. Transistors M
1
and M
2
buffer input data signal
102
when clock signal
104
is high, and transistors M
3
and M
4
store the data buffered by transistors M
1
and M
2
when clock signal
104
is low.
As shown in
FIG. 1
, transistors in the four transistor levels are connected in series (the source of the transistor in a previous level is connected to the drain of the transistor in the next level). The number of series-connected transistors dictates the minimum power supply voltage (VDD) required for proper operation of circuit
100
. In practical applications, the power supply voltage is fixed, thus limiting the number of series-connected transistors that can be deployed in circuit
100
.
BRIEF SUMMARY OF THE INVENTION
A differential latch circuit according to an example embodiment includes a differential reset function implemented with no more than three levels of series-connected transistors. With this configuration, the latch circuit can be deployed in applications having low voltage power supplies, relative to conventional latch circuits that require additional levels of transistors.
The above and other aspects of the present invention may be carried out in one form by a differential latch circuit comprising a first arrangement of transistors configured to perform a latch function, in response to a differential latch input and a differential clock signal, that provides a differential latch output, and a second arrangement of transistors connected to the first arrangement of transistors, the second arrangement of transistors being configured to perform a reset function, in response to a differential reset voltage, that drives the differential latch output to a logic low state. In this embodiment, the first arrangement of transistors includes a maximum of three levels of series-connected transistors, and the second arrangement of transistors includes a maximum of three levels of series-connected transistors.


REFERENCES:
patent: 5172011 (1992-12-01), Leuthold et al.
patent: 5349554 (1994-09-01), Delker
patent: 5488319 (1996-01-01), Lo
patent: 5508648 (1996-04-01), Banik
patent: 5576644 (1996-11-01), Pelella
patent: 5850155 (1998-12-01), Matsumoto
patent: 5900760 (1999-05-01), Lee
U.S. 2003/0160644A1, “High Speed Fully Balanced Differential Flip Flop With Reset” by Ling, Aug. 28, 2003.

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