Reset circuit of semiconductor circuit

Details Reset circuit of semiconductor circuit Reset circuit of semiconductor circuit

2001-06-29

2004-02-10

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S142000, C327S538000

Reexamination Certificate

active

06690220

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a reset circuit for reliably resetting plural circuits to be reset, which are included in a semiconductor circuit.
BACKGROUND OF THE INVENTION
A structure of a prior art reset circuit for resetting a semiconductor circuit will be described with reference to FIG.
8
. To simplify the description, assume here that the number of plural circuits to be reset, i.e., reset target circuits in the semiconductor circuit is three.
As shown in
FIG. 8
, the prior art reset circuit is constituted by a reset terminal
100
, a filter circuit
110
, and first to third reset target circuits
241
to
243
. A reset terminal input reset signal S
100
which is input to the reset terminal
100
is input to the first to third reset target circuits
241
to
243
via the filter circuit
110
, respectively, and resets the respective reset target circuits
241
to
243
.
The filter circuit
110
is constituted by a low-pass filter
111
for eliminating high frequency components of a signal, and a Schmitt amplifier
112
for shaping the waveform of the signal from which the high frequency components have been eliminated by the low-pass filter
111
. The filter circuit
110
eliminates the high frequency components of the reset terminal input reset signal S
100
which is input from the reset terminal
100
to shape the waveform, thereby preventing the reset operation from being erroneously activated by noises which are input to the reset terminal
100
.
Wiring between the filter circuit
110
and the reset target circuits
241
to
243
is accompanied by parasitic impedances
131
to
133
, respectively, which are generated according to resistance components or capacitance components depending on the wiring, and contribute to blunting of the waveform of a reset start signal S
210
which is output from the filter circuit
110
. When the wave form of the reset start signal S
210
is blunted, not all of the reset target circuits
241
to
243
can be reset, and only part of the reset target circuits are reset, there is a case for example where the third reset target circuit
243
cannot be reset while the reset start signal S
210
is rising as shown in FIG.
9
.
Hereinafter, with reference to FIGS.
9
(
a
)~
9
(
f
), descriptions will be given of the operation of the reset circuit in a case where the reset terminal input reset signal S
100
having a short pulse length due to surge noises or the like is input to the reset terminal
100
of the semiconductor circuit, and part of the plural reset target circuits
241
to
243
in the semiconductor circuit is not reset. FIGS.
9
(
a
)~
9
(
f
) are signal timing charts for explaining the operation of the prior art reset circuit.
In
FIG. 9
, the same reference numerals as those in
FIG. 8
denotes the same signals.
Initially, at time t
11
, the reset terminal input reset signal S
100
(FIG.
9
(
a
)) rises. With its rising, at time t
12
, a low-pass filter output reset signal S
111
(FIG.
9
(
b
)) which has passed through the low-pass filter
111
becomes higher than an upper threshold Vshh constituting a hysteresis of the Schmitt amplifier
112
, and the reset start signal S
210
(FIG.
9
(
c
)) turns into H level.
Then, at time t
13
, the reset terminal input reset signal S
100
falls. With its falling, at time t
14
, the low-pass filter output reset signal S
111
which has passed through the low-pass filter
111
becomes lower than the level of a lower threshold Vshl constituting the hysteresis of the Schmitt amplifier
112
, and the reset start signal S
210
turns into L level.
This reset start signal S
210
is blunted in different manners which vary with the properties of the resistances and capacitances of the parasitic impedances
131
to
133
before the signal is input to the first to third reset target circuits
241
to
243
, and it is input to the reset target circuits
241
to
243
for example with the signal waveforms of the reset signals S
210
a
to S
210
c
as shown in FIGS.
9
. To be specific, in
FIG. 8
, with regard to the parasitic impedances
131
to
133
, the longer the wring lengths from the filter circuit
110
to the reset target circuits are, the larger the resistances and the capacitances are, respectively, and thus the waveform of the input signal is more blunted. In
FIG. 9
, it is shown by the waveforms of the reset signals S
210
a
to S
210
c
that the parasitic impedance
131
is the lowest and the parasitic impedance
133
is the highest.
The reset signal S
210
a
which has been input to the first reset target circuit
241
exceeds a threshold Vth for the reset operation at time t
25
, and then the first reset target circuit
241
performs the reset operation. Similarly, with regard to the second reset target circuit
242
, the reset signal S
210
b
exceeds the threshold Vth for the reset operation at time t
26
, and thus the reset operation is performed. However, with regard to the third reset target circuit
243
, since the reset signal S
210
c
does not exceed the threshold Vth for the reset operation by the time t
14
when the reset start signal S
210
falls, the reset operation of the third reset circuit
243
is not performed.
In order to prevent the plural reset target circuits
241
to
243
in the semiconductor circuit from being partially reset as described above, the passband of the low-pass filter
111
is set narrower when the high frequency components of the signal are eliminated in the low-pass filter
111
, or the hysteresis (range from Vshh to Vshl) of the Schmitt amplifier
112
is set larger.
However, since the parasitic impedance is increased with the miniaturization of the semiconductor circuit or an increase in the circuit scale in recent years, when the low-pass filter
111
is designed correspondingly to the parasitic impedance, the chip size of the semiconductor circuit is increased. In addition, in recent years, the power voltage of the semiconductor circuit is decreased, whereby the power voltage is diversified. Thus, it is difficult to design the Schmitt amplifier
112
so as to have a larger hysteresis.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a reset circuit of a semiconductor circuit, which does not partially reset a semiconductor circuit having plural reset target circuits but can reliably reset the semiconductor circuit even when a surge noise having a shorter pulse length or the like is input to the reset terminal.
Other objects and advantages of the present invention will become apparent from the detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a 1st aspect of the present invention, there is provided a reset circuit of a semiconductor circuit including a first plurality of all reset target circuits, each circuit for being reset by a reset instruction signal, and each circuit for outputting a respective reset completion signal when reset by the reset instruction signal, wherein at least one of the first plurality of reset target circuits comprises an N-bit counter; and a reset instruction signal control means for receiving a reset start signal, outputting the reset instruction signal in response to the reset start signal, and controlling a timing for deactivating the reset instruction signal, in accordance with the reset completion signals, wherein the first plurality of reset target circuits are for outputting respective reset completion signals when the respective reset target circuits are reset by the reset instruction signal, and the reset instruction signal control means is for deactivating the reset instruction signal when all of the reset completion signals from the first plurality of reset target circuits are activated. According to a 2nd aspect of the present invention, there is provided a reset circuit of a semiconductor circuit including plural reset target circuits, the res

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