Reset circuit for a pipelined signal processor

Details Reset circuit for a pipelined signal processor Reset circuit for a pipelined signal processor

1995-05-11

1996-09-24

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327198, H03K 3037

Patent

active

055594581

ABSTRACT:
Briefly, in accordance with one embodiment of the invention, a method of reducing the power consumption of a pipelined signal processor embedded in an integrated circuit (IC), after applying power to the IC, comprises the step of: applying a sufficient number of internally generated clock pulses to the pipelined signal processor so as to place at least one bus in the signal processor pipeline in a predetermined state. Briefly, in accordance with another embodiment of the invention, an integrated circuit comprises: a power-up reset circuit for a pipelined signal processor. The power-up reset circuit includes a counter and a digital signal oscillator. The digital signal oscillator and counter are coupled in a configuration so as to provide a predetermined number of clock pulses substantially in response to a power-up signal. The configuration is adapted to be coupled to the pipelined signal processor.

REFERENCES:
patent: 5414307 (1995-05-01), Brandmaier
Microprocessors and Microsystems, Jun. 1994, vol. 18, No. 5, "Microprocessor Supervisory Circuits," pp. 291-296.

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