Reset circuit for a peripheral component interconnect bus

Details Reset circuit for a peripheral component interconnect bus Reset circuit for a peripheral component interconnect bus

1996-08-20

1999-02-02

An, Meng-Ai T.

395306, G06F 1300

Patent

active

058676767

ABSTRACT:
A reset circuit for a computer system having PCI chip set, the reset circuit for resetting a PCI data bus in the event of a warm boot in the computer system to prevent corrupt data files, the reset circuit including a logical AND gate with a first input connected to a cold boot reset pin of the PMC, and an output connected to a PCI data bus; a logical OR gate with a first input connected to the flush pin of the PMC and an output connected to a second input of the logical AND gate; an inverter with an input connected to the flush pin of the PMC; and a delay device connected between an output of the inverter and a second input of the logical OR gate.

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patent: 5657455 (1997-08-01), Gates et al.
patent: 5675794 (1997-10-01), Meredith
"60x Bus-to-PCI Bridge" IBM Technical Disclosure Bulletin; vol. 38, No. 5, May 1995, New York, U.S.; pp. 401-102.
Shanley & Anderson: "PCI System Architecture", Nov. 1995, Addison-Wesley, Amsterdam, NL *p. 440, paragraph 5--p. 441, paragraph 1: figures 19-19*.
Article: Andrews, Warren; "Computer Design"; vol. 31; No. 8; Aug. 1992; pp. 42-45.
Article: Davy, Tom; "Intel's Natoma offers better performance for NT"; PC Week OnLine; May 3, 1996; pp. 1-3.

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