Reset circuit

Details Reset circuit Reset circuit

1994-10-28

1996-02-06

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327143, 327198, H03L 700

Patent

active

054898633

ABSTRACT:
A test signal generator outputs a test signal synchronized with the data transmission of the CPU. The test signal is supplied concurrently to a comparator and to an input unit. The output signal of the input unit is then supplied to a line of an bus signal to be stored in a first storage unit. On the line of the bus signal, there is provided an LPF consisting of an resistance and an capacity. When transmission of the bus signal is delayed, the output signal of the comparator changes according to the timing of a clock. The changed output signal is immediately stored in a second storage unit to output a reset signal, thereby resetting the CPU.

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patent: 5159205 (1992-10-01), Gorecki et al.
patent: 5220673 (1993-06-01), Dalrymple et al.
patent: 5377205 (1994-12-01), Shi

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