Reset and synchronization interface circuit

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

370100, H04L 700

Patent

active

048037028

ABSTRACT:
A reset and synchronization interface circuit for use in a subscriber power controller includes a reset circuit portion and a synchronization circuit portion. The reset circuit portion is formed of a first comparator, a second comparator, and an output network for generating a reset signal. The first comparator compares an input signal with the reference voltage to produce a first output signal and a second output signal. The second comparator compares the first output signal from the first comparator with the reference voltage to produce a third output signal. The output network inverts and shifts the level of the third output signal to produce the reset signal. The synchronization circuit portion is formed of a third comparator and an AND logic gate for generating a modified synchronizing signal. The third comparator inverts a synchronizing clock signal to generate a complementary synchronizing clock signal. The AND logic gate combines logically the second output signal from the first comparator with the complementary synchronizing clock signal to produce the modified synchronizing signal.

REFERENCES:
patent: 3798555 (1974-03-01), Tempka et al.
patent: 4503490 (1985-03-01), Thompson
patent: 4549100 (1985-10-01), Spence

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