Reset and pulse width control circuits for high-performance mult

Details Reset and pulse width control circuits for high-performance mult Reset and pulse width control circuits for high-performance mult

1995-06-06

1997-04-01

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327198, 327291, 327295, H03K 301

Patent

active

056170475

ABSTRACT:
A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.

REFERENCES:
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patent: 5252867 (1993-10-01), Sorrells et al.
patent: 5467037 (1995-11-01), Kumar et al.
patent: 5498989 (1996-03-01), Diba
T.I. Chappell et al, "A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM . . . ", IEEE J.Solid State Circuits, V26, #11, pp. 1577-1585 Nov. 1991.

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