Resequencing system

Details Resequencing system Resequencing system

1994-08-10

1996-01-09

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 601, 370 61, 370 942, H04L 1256

Patent

active

054835232

ABSTRACT:
A resequencing system (DDM, TSG, IC, REG, SUB, RSU) is disclosed for resequencing the cells of a cell stream transmitted through the cascaded connection of a first switching node (SN'), a buffer register (OB) and a second switching node (SN). It includes: a resequencing means (TSG, IC, REG, SUB, RSU) associated to the second switching node (SN), a delay measurement circuit (DDM) associated with the buffer register (OB) and adapted to measure the time delay to which each of said cells is submitted in said buffer register (OB), means to communicate the delay thus measured for each cell to the resequencing means (TSG, IC, REG, SUB, RSU). After said cell has been switched by said second switching node (SN), the resequencing means (TSG, IC, REG, SUB, RSU) submits this cell to a time delay equal to the difference between a predetermined constant time delay value and the communicated delay.

REFERENCES:
patent: 5127000 (1992-06-01), Henrion
patent: 5173897 (1992-12-01), Schrodi et al.
patent: 5253251 (1993-10-01), Aramaki
patent: 5260935 (1993-11-01), Turner
`Design and Technology Aspects of VLSI's for ATM Switches` by T R Banniza e.a., IEEE Journal on Selected Areas in Communications, vol. 9, No. 8, Oct. 1991, pp. 1255-1264.

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