Multiplex communications – Wide area network – Packet switching
Patent
1993-11-12
1995-05-09
Marcelo, Melvin
Multiplex communications
Wide area network
Packet switching
370 61, 370 941, H04L 1256
Patent
active
054147050
ABSTRACT:
The application is for telecommunication networks of asynchronous transfer mode. The device contains a time stamp generator (TSG) for assigning a time stamp to each cell; a buffer memory (BM); an address memory (FSAM) for memorizing the address of the first sub-cell of each cell; a link memory (LM); and a circuit for indicating the address of the buffer memory that contains the first sub-cell of a cell. This circuit contains in particular: a memory that is accessible by its content, for memorizing a cell identifier (TSTP-OA; TSTP-OM) when a cell is made to wait, where each identifier indicates a time period during which the waiting delay expires, and at least one output from which the cell must be emitted; and a marker memory for each output, where a marker is recorded as soon as a cell is made to wait, to locate the time period during which the waiting delay of this cell will expire; the markers are read starting with the oldest, and only those that correspond to expired delays are validated when the output in question indicates that it is available; and each marker is potentially common to several cells.
REFERENCES:
patent: 5127000 (1992-06-01), Henrion
patent: 5214639 (1993-05-01), Henrion
patent: 5237564 (1993-08-01), Lespagnol et al.
patent: 5278825 (1994-01-01), Wallmeier et al.
patent: 5297140 (1994-03-01), Boyer et al.
Guebels Pierre-Paul F. M. M.
Therasse Yves
ALCATEL N.V.
Marcelo Melvin
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