Reprogrammable read only variable threshold transistor memory wi

Details Reprogrammable read only variable threshold transistor memory wi Reprogrammable read only variable threshold transistor memory wi

1974-06-10

1976-07-20

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307279, 307303, 357 47, G11C 506, G11C 1140

Patent

active

039710017

ABSTRACT:
A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

REFERENCES:
patent: 3618051 (1971-11-01), Oleksiak
patent: 3733591 (1973-05-01), Cricchi
patent: 3747072 (1973-07-01), Lodi et al.
patent: 3836894 (1974-11-01), Cricchi
patent: 3858060 (1974-12-01), Kenyon

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