Reprogrammable memory device with variable page size

Details Reprogrammable memory device with variable page size Reprogrammable memory device with variable page size

1997-12-16

1999-11-23

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518529, 36523006, G11C 1604

Patent

active

059911964

ABSTRACT:
An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.

REFERENCES:
patent: 5297096 (1994-03-01), Terada et al.
patent: 5347486 (1994-09-01), Urai
patent: 5428580 (1995-06-01), Kawashima et al.
patent: 5600601 (1997-02-01), Murakami et al.

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