Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1999-01-13
2002-02-26
Le, Amanda T. (Department: 2734)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C386S349000, C360S062000
Reexamination Certificate
active
06351507
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a reproducing apparatus and more particularly to a reproducing apparatus arranged to be capable of generating a clock signal synchronized in phase with reproduced data.
2. Description of Related Art
The reproducing apparatuses of the above-stated kind include digital VTRs which are arranged to record and reproduce video signals in the form of digital signals on and from magnetic tapes. The digital VTRs are being developed not only for broadcasting stations but also for home use. The home-use digital VTRs obtain video images mainly from TV broadcast. However, other sources of video images have come to be often used, including the analog VTRs of VHS and 8-mm systems, personal computers, TV games, etc.
In extracting a clock signal from a data train being received by an apparatus which transmits data at a high speed, such as a digital VTR, it is known to use a phase-locked loop (hereinafter referred to as PLL) which is arranged as shown in FIG.
1
.
Referring to
FIG. 1
, a phase difference between reproduced data and a clock signal is detected by a phase comparison circuit
701
. A low-pass filter (hereinafter referred to as LPF)
702
filters a signal indicative of the phase difference thus obtained by the phase comparison circuit
701
, and the filtered signal is supplied to a voltage-controlled oscillator (hereinafter referred to as VCO)
703
as a control signal. The VCO
703
generates a clock signal having a frequency corresponding to the voltage of the control signal. A frequency divider
704
then frequency-divides the clock signal outputted from the VCO
703
and feeds the frequency-divided clock signal back to the phase comparison circuit
701
.
However, in all the apparatuses mentioned above, PLL circuits employed for generating a clock signal are configured as analog circuits. The analog circuits are apt to have their characteristics vary with variations of ambient conditions such as temperature, aging, etc., and thus result in an unstable clock signal generating action.
Meanwhile, the digital VTRs are also required, like in the case of analog VTRS, to have special reproducing functions such as fast feeding, slow reproduction, etc. However, in carrying out such a special reproducing function, the relative speed of a head to a tape vary to cause variations in frequency of the reproduced signal. If the frequency of the reproduced signal varies too much, the frequency comes out of the lock range of the PLL, thereby making it impossible to obtain an adequate clock signal.
Further, for obtaining more appropriate data, the digital VTR is provided with an equalizer for equalizing the waveform of the reproduced signal. However, if the equalizing characteristic of the equalizer is fixedly set to obtain an optimum waveform for normal reproduction, the amount of errors in reproduced data increases to deteriorate picture quality in the event of a special reproduction, since the frequency of the reproduced signal varies during the special reproduction, as mentioned above, and the set characteristic is not appropriate for the special reproduction.
Further, the video signals obtained from the video image sources of varied kinds mentioned above sometimes have variations of time base to such a degree that the video signals are hardly considered to be standard signals. However, the frequency variable ranges of crystal oscillators hitherto used for digital VTRs as recording operation clock signal generating circuits have been too narrow for processing the input video signals of varied kinds mentioned above. This problem may be solved by providing an additional VCO for recording. However, the provision of the additional VCO results in an increase in the number of parts and is, therefore, against a desired reduction in cost and size.
SUMMARY OF THE INVENTION
This invention is directed to the solution of the problems of the prior art described above.
It is, therefore, an object of this invention to provide a reproducing apparatus arranged to be capable of generating an operation clock signal which is apposite to any input signal, without increasing the number of parts.
Under this object, a clock signal generating device arranged according to this invention as an embodiment thereof comprises generating means for generating a clock signal, a first loop including phase difference detecting means for detecting a phase difference between the clock signal and input data and a filter for filtering an output of the phase difference detecting means and feeding back the filtered output to the generating means, a second loop including computation means for obtaining a difference between a frequency of the clock signal and a target frequency and accumulation means for accumulating an output of the computation means and feeding back the accumulated output to the generating means, and control means for manually controlling whether or not the first loop is to be operated.
It is another object of this invention to provide a reproducing apparatus arranged to stably generate a clock signal without being affected by variations of temperature, variations caused by aging, etc., and to have an adequate equalizing characteristic.
Under that object, a reproducing apparatus according to this invention as another embodiment thereof comprises generating means for generating a clock signal, frequency detecting means for detecting a difference between a frequency of the clock signal generated by the generating means and a predetermined frequency, equalizing means for equalizing reproduced data, an equalizing characteristic of the equalizing means being controlled according to an output of the frequency detecting means, and phase difference detecting means for detecting a phase difference between the clock signal generated by the generating means and the reproduced data, a clock signal generating operation of the generating means being controlled according to the output of the frequency detecting means and an output of the phase difference detecting means.
These and further objects and features of this invention will become apparent from the following detailed description of embodiments thereof taken in connection with the accompanying drawings.
REFERENCES:
patent: 5600501 (1997-02-01), Yamakoshi et al.
patent: 6041161 (2000-03-01), Okamoto et al.
Sasaki Hana
Sasaki Yoshiyuki
Tanaka Yasuyuki
Canon Kabushiki Kaisha
Le Amanda T.
Robin Blecker & Daley
Sasaki Hana
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