Reporting delay in modeling environments

Details Reporting delay in modeling environments Reporting delay in modeling environments

2009-06-01

2011-11-08

Rodriguez, Paul (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C703S013000

Reexamination Certificate

active

08055494

ABSTRACT:
Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of the model is determined and reported to users before executing the model. The delay of each component of the model may be determined based on intrinsic information of the component. If the intrinsic information of the component does not provide information on the delay of the component, the component may be simulated to determine the delay of the components. The model may be automatically compensated for the delay. The delay is reported prior to the execution of the model, and compensated for without executing the model.

REFERENCES:
patent: 4667240 (1987-05-01), Willis et al.
patent: 6311147 (2001-10-01), Tuan et al.
patent: 7219048 (2007-05-01), Xu
patent: 2004/0208193 (2004-10-01), Orofino et al.
Lee, James M., Verilog® Quickstart, 3rd Edition, A Practical Guide to Simulation and Synthesis in Verilog, pp. 55, 338 (2002).
The Math Works, Simulink® Model-Based and System-Based Design, Using Simulink, Version 4, (2001).

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