Patent
1993-03-08
1995-12-12
Bowler, Alyssa H.
39520012, G06F 1314
Patent
active
054758165
ABSTRACT:
In a computer network, at least one of the computers transmits a request packet to a destination urge a reply packet therefrom. A decoder is provided to determine the identity of a destination from which a reply packet is received and, in response, generates a reply interrupt command. A microprocessor is responsive to the reply interrupt command for performing a reply interrupt routine. First and second reply monitor circuits are associated respectively with other computers. Each of the reply monitor circuits comprises a flag arranged to be set when a request packet is transmitted from the microprocessor to another computer with which the reply monitor circuit is associated and arranged to be reset by the decoder when a reply packet is received from the another microprocessor-based system. A timer is activated in response to the flag being set for measuring the amount of time and deactivated in response to the flag being reset. The timer applies a time-out interrupt command to the microprocessor when a predetermined amount of time has elapsed to cause it to perform a time-out interrupt routine.
REFERENCES:
patent: 4912723 (1990-03-01), Verbanets, Jr.
patent: 5134691 (1992-07-01), Elms
Inoue Yasushi
Yonezawa Naomichi
Bowler Alyssa H.
Kyle Charles
NEC Corporation
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