Replica network for linearizing switched capacitor circuits

Details Replica network for linearizing switched capacitor circuits Replica network for linearizing switched capacitor circuits

2001-07-25

2004-04-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S558000, C327S337000

Reexamination Certificate

active

06720799

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a replica network for linearizing switched capacitor circuits.
2. Background Art
Switched capacitor sampling networks are commonly used in signal processing applications. They can be efficiently implemented using CMOS technology and are easily integrated with other networks. Among other functions, switched capacitor sampling networks are used for filtering, sample and hold, analog-to-digital conversion, and digital-to-analog conversion.
High performance switch capacitor sampling networks are typically configured as differential circuits. As compared with single-ended designs, a differential embodiment enjoys improved power supply noise rejection, double the output range, and cancellation of even-order distortion components.
FIG. 1A
is a schematic diagram of a typical differential switched capacitor sampling network
100
. In
FIG. 1A
, network
100
comprises eight switches: S
1
102
, S
2
104
, S
3
106
, S
4
108
, S
5
110
, S
6
112
, S
7
114
, and S
8
116
. Collectively, S
1
102
, S
2
104
, S
3
106
, and S
4
108
are referred to as signal conducting switches, while S
5
110
, S
6
112
, S
7
114
, and S
8
116
are collectively referred to as summing junction switches.
FIG. 1B
illustrates a two-phase nonoverlapping clock scheme
118
defined by four clock waveforms: &phgr;
1
120
, &phgr;
1D
122
, &phgr;
2
124
and &phgr;
2D
126
. The position of each switch at any given time is determined by its corresponding clock waveform. In a representative embodiment, a switch is open when its corresponding clock waveform is “off” and closed when its corresponding clock waveform is “on.” One skilled in the art would recognize that network
100
could be configured with other relationships between the state of the switches and their corresponding clock waveforms.
Clock scheme
118
is configured so that &phgr;
1
120
and &phgr;
1D
122
are on when &phgr;
2
124
and &phgr;
2D
126
are off. Clock waveforms &phgr;
1D
122
and &phgr;
2D
126
are similar to, respectively, clock waveforms &phgr;
1
120
and &phgr;
2
124
. However, the falling edges of &phgr;
1D
122
and &phgr;
2D
126
are not initiated until after &phgr;
1
120
and &phgr;
2
124
have returned to their “off” states. Together, clock waveforms &phgr;
1
120
and &phgr;
1D
122
define a sampling phase of clock scheme
118
while clock waveforms &phgr;
2
124
and &phgr;
2D
126
define a transferring phase.
Network
100
further comprises a positive voltage sampling capacitor C
1
+
128
, a negative voltage sampling capacitor C
1
−
130
, and a differential integrator
132
. Differential integrator
132
comprises an operational amplifier
134
with an inverting terminal T
−
136
, a noninverting terminal T
+
138
, a positive voltage output signal V
o
+
140
, and a negative voltage output signal V
o
−
142
. A positive voltage feedback capacitor C
2
+
144
is connected in parallel with operational amplifier
134
between T
−
136
and V
o
+
140
. A negative voltage feedback capacitor C
2
−
146
is connected in parallel with operational amplifier
134
between T
+
138
and V
o
−
142
. Both a positive voltage input signal V
i
+
146
and a negative voltage input signal V
i
−
148
are received by network
100
.
Switch S
1
102
is disposed between V
i
+
146
and C
1
+
128
. Switch S
2
104
is disposed between V
i
−
148
and C
1
+
128
, such that S
1
102
and S
2
104
are connected in parallel with each other at a node N
1
150
upstream of C
1
+
128
. Switch S
3
106
is disposed between V
i
+
146
and C
1
−
130
. Switch S
4
108
is disposed between V
i
−
148
and C
1
−
130
, such that S
3
106
and S
4
108
are connected in parallel with each other at a node N
2
152
upstream of C
1
−
130
.
Switch S
5
110
is disposed between a node N
3
154
downstream of C
1
+
128
and T
−
136
. Switch S
6
112
is disposed between N
3
154
and an analog ground connection
156
. Switch S
7
114
is disposed between a node N
4
158
downstream of C
1
−
130
and T
+
138
. Switch S
8
116
is disposed between N
4
158
and analog ground connection
156
.
Operation of network
100
can be explained by tracing the circuits that are established in response to the cycling of the clock waveforms of clock scheme
118
.
At a time t
0
, clock waveforms &phgr;
1
120
and &phgr;
1D
122
cycle to the on state while clock waveforms &phgr;
2
124
and &phgr;
2D
126
remain in the off state. In response to the on state of &phgr;
1
120
, switches S
6
112
and S
8
116
close. In response to the on state of &phgr;
1D
122
, switches S
1
102
and S
4
108
close. With S
1
102
and S
6
112
closed, a circuit is established between V
i
+
146
and analog ground
156
through C
1
+
128
. This circuit allows V
i
+
146
to be sampled as a charge on an upstream plate P
1u
+
160
of C
1
+
128
. The value of this charge is equal to the product of the capacitance of C
1
+
128
and the voltage of V
i
+
146
. Likewise, with S
4
108
and S
8
116
closed, a circuit is established between V
i
+
148
and analog ground
156
through C
1
−
130
. This circuit allows V
i
−
148
to be sampled as a charge on an upstream plate P
1u
−
162
of C
1
+
130
. The value of this charge is equal to the product of the capacitance of C
1
−
130
and the voltage of V
1
−
148
.
At a time t
1
, clock waveform &phgr;
1
120
cycles to the off state, while &phgr;
1D
122
remains in the on state. Clock waveforms &phgr;
2
124
and &phgr;
2D
126
remain in the off state. In response to the off state of &phgr;
1
120
, switches S
6
112
and S
8
116
open. Opening switch S
6
112
breaks the circuit between V
1
+
146
and analog ground
156
. This isolates the charge stored on upstream plate P
1u
+
160
, thus effectively sampling V
i
+
146
. Likewise, opening switch S
8
116
breaks the circuit between V
i
−
148
and analog ground
156
. This isolates the charge stored on upstream plate P
1u
−
162
, thus effectively sampling V
i
−
148
.
At a time t
2
, clock waveform &phgr;
1D
122
cycles to the off state. Clock waveforms &phgr;
1
120
, &phgr;
2
124
, and &phgr;
2D
126
remain in the off state. In response to the off state of &phgr;
1D
122
, switches S
1
102
and S
4
108
open. By delaying the opening of switches S
1
102
and S
4
108
until after switches S
6
112
and S
8
116
have been opened, and thus isolating the charges stored on C
1
+
128
and C
1
−
130
, the sampled signals are unaffected by the charge injection that occur after switches S
6
112
and S
8
116
have been opened. Particularly, the sampled signals are not distorted by any charge injection resulting from the opening of switches S
1
102
and S
4
108
.
At a time t
3
, clock waveforms &phgr;
2
124
and &phgr;
2D
126
cycle to the on state while clock waveforms &phgr;
1
120
and &phgr;
1D
122
remain in the off state. In response to the on state of &phgr;
2
124
, switches S
5
110
and S
7
114
close. In response to the on state of &phgr;
2D
126
, switches S
2
104
and S
3
106
close. With S
2
104
and S
5
110
closed, a circuit is established between V
i
−
148
and differential integrator
132
through C
1
+
128
. This circuit enables the charge on upstream plate P
1u
+
160
to be transferred to differential integrator
132
. One skilled in the art would recognize that the transferred charge is defined by Eq. (1):
Q=C
s
×[V
i
+
−V
i
−
],  Eq. (1)
where C
s
equals the value of the capacitance of C
1
+
128
. As it is desired that the charge transferred to differential integrator
132
equals the charge stored on capacitor C
1
+
128
, the use of a differential circuit enables C
1
+
128
to h

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