Boots – shoes – and leggings
Patent
1988-03-01
1990-11-27
Anderson, Lawrence E.
Boots, shoes, and leggings
3408255, 3642402, 364239, G06F 1336, G06F 1340
Patent
active
049741535
ABSTRACT:
A system for implementing a repeater interlock scheme between a first and a second bus utilizes two repeaters. The first repeater coupled to the first bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second repeater which is coupled to memory through the second bus. The transaction buffer passes the interlock data for memory to the second bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the second bus.
REFERENCES:
patent: 4484267 (1984-11-01), Fletcher
patent: 4604689 (1986-08-01), Burger
Natusch Paul J.
Pimm David W.
Silver Robert T.
Anderson Lawrence E.
Digital Equipment Corporation
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