Repairable thin film transistor matrix substrate having...

Details Repairable thin film transistor matrix substrate having... Repairable thin film transistor matrix substrate having...

1998-01-22

2001-07-10

Parker, Kenneth (Department: 2871)

Liquid crystal cells, elements and systems

Particular excitation of liquid crystal

Electrical excitation of liquid crystal

C349S197000, C349S054000

Reexamination Certificate

active

06259494

ABSTRACT:

The present invention relates to a thin film transistor matrix substrate for driving a liquid crystal display, and more particularly, to a thin film transistor matrix substrate having electrodes for repairing bus line disconnections and interlayer short-circuits, and to a method for repairing such thin film transistor matrix substrates.
BACKGROUND OF THE INVENTION
A conventional thin film transistor matrix substrate is described herein with reference to
FIGS. 14A and 14B
.
FIG. 14A
shows a plan view of a portion of a conventional TFT matrix substrate
100
including a plurality of gate bus lines
101
(two shown) extending in a lateral direction or X-direction and a plurality of drain bus lines
103
(two shown) extending in a vertical direction or Y-direction. These bus lines
101
,
103
are formed on a transparent substrate
100
A. In the areas where the gate and drain bus lines
101
,
103
cross, the bus lines are electrically insulated from each other by an insulated film (not shown). An accumulated capacitance bus line
102
is provided between each pair of adjacent gate bus lines
101
so that it extends substantially parallel to the gate bus lines
101
. A constant ground potential, for example, is applied to the accumulated capacitance bus lines
102
. The accumulated capacitance and the drain bus lines
102
,
103
are also insulated from each other by an insulation film (not shown) in the areas where they cross.
A thin film transistor (TFT)
104
is formed approximately at each crossing point of the gate and the drain bus lines
101
,
103
, and includes a drain electrode
104
D, a source electrode
104
S and a gate electrode (not shown). The drain electrodes
104
D of the TFTS
104
in a single column are all connected to a corresponding drain bus line
103
, and the gate electrodes (not shown) are connected to a corresponding gate bus line, which in effect, work as the gate electrodes. A pixel electrode
105
(shown in dotted lines) corresponding to each TFT
104
is arranged in a generally rectangular region surrounded by the corresponding gate and drain bus lines
101
,
103
, and is connected to the source electrode
104
S via an opening
107
though an insulated film (not shown) between the pixel electrode
105
and the TFT
104
.
The TFT matrix substrate
100
also includes a pair of auxiliary capacitance electrodes
106
which extend from each of the accumulated capacitance bus lines
102
between each pair of drain bus lines
103
. Each of the auxiliary capacitance electrodes
106
extends outwardly in the opposite vertical directions, i.e., in the positive and negative Y-directions, near the corresponding pair of gate bus lines
101
. The pair of auxiliary capacitance electrodes
106
are arranged so that each is adjacent and generally parallel to one of the pair of the corresponding drain bus line
103
and partially overlaps with one side of the pixel electrode
106
. A liquid crystal material (not shown) is held between two common electrode substrates (not shown) which are also provided on the TFT substrate matrix substrate
100
. In this manner, an auxiliary capacitance C
s
(best seen in
FIG. 14B
) is formed between the accumulated capacitance bus line
102
and the pixel electrode
105
.
FIG. 14B
is an electrical circuit equivalent of the TFT matrix substrate
100
of
FIG. 14A
, and shows that a liquid crystal capacitance C
LC
is formed between the pixel electrode
105
and the accumulated capacitance electrode
102
, and the auxiliary capacitance C
S
is formed in parallel with the liquid crystal capacitance C
LC
. Moreover, a floating capacitance C
NS
is formed between the pixel electrode
105
and drain bus line
103
.
When the TFT
104
is not conductive, as when a particular display pixel of the liquid crystal display is not selected, the potential of the corresponding drain bus line
103
changes significantly. As a result, the potential of the relevant pixel electrode
105
also changes, due to the capacitance coupling by the floating capacitance C
NS
. The resulting voltage variation &Dgr;V in the pixel electrode
105
is expressed as follow:
&Dgr;
V=C
NS
/(
C
NS
+C
LC
+C
S
)  (1)
The potential variation creates an unwanted gradient of brightness along the scanning direction (direction parallel to the drain bus lines
103
) of the display pixels, and crosstalk (uneven brightness), depending on the display pattern.
In the TFT matrix substrate
100
shown in
FIG. 14A
, the accumulated capacitance bus lines
102
and auxiliary capacitance electrode
106
are provided to increase the auxiliary capacitance electrode C
S
, thereby reducing the negative influence of the voltage variation of the drain bus lines
103
and enhancing the display quality. In other words, the voltage variation is reduced by inserting the auxiliary capacitance C
S
in parallel with the liquid crystal capacitance C
LC
(best seen in FIG.
14
B).
As shown in
FIG. 14A
, the auxiliary electrode capacitances
106
are arranged adjacent the drain bus lines
103
to obtain a large aperture ratio. However, this arrangement at times results in the auxiliary capacitance electrode
106
and drain bus lines
103
being short-circuited, due, for example, to a defective insulated film between these elements or because of alignment errors of patterns of the auxiliary capacitance electrodes
106
and the drain bus lines
103
. Further, a short-circuit may also occur between the drain and the gate bus lines
103
,
101
, and between the drain bus lines and the accumulated capacitance bus lines
102
. Moreover, disconnections or cuts on the bus lines
101
,
102
,
103
may also occur as a result of dust or foreign matters generated during the formation of the electrode and the bus patterns or as a result of a flawed mask, etc.
If the above-described interlayer short-circuits or disconnections of bus lines are generated even at one point, the entire TFT matrix substrate could be considered defective. Therefore, the ability to repair such faults during the manufacturing stage is important in improving manufacturing yield.
A known method of repairing the short-circuits or the disconnections described above is explained with reference to
FIG. 15
, which shows a schematic plan view of the conventional TFT matrix substrate
100
. The TFTs
104
and the pixel electrodes
105
are arranged in the form of a matrix, and a plurality of backup lines
108
,
109
(only one each shown in
FIG. 15
) are arranged in the upper and lower peripheral areas.
In operation, if a disconnection Bo occurs on the drain bus line
103
, a repair is performed by connecting both the backup lines
108
,
109
, which are electrically connected to an external circuit, to the disconnected drain bus lines
103
at two disconnection repairing points Wo and Woo, respectively. In this manner, the backup lines
108
,
109
carry the signals which otherwise would have been carried by the disconnected drain bus line
103
. The connections at the repairing points Wo and Woo is made by dissolving the insulated and the metal films with irradiation of a laser beam.
One disadvantage of the above-described repair method is that noise is superimposed onto the backup lines
108
,
109
due to capacitance coupling, which arises as a result of the backup lines
108
,
109
crossing the drain bus lines
103
and being separated from the drain bus lines by an insulated film. To reduce the effect of such noise, the resistance of the backup bus lines
108
,
109
could be lowered, which would require widening the width of the bus lines. However, an increase in the width of the bus lines in turn results in an increase in the probability of interlayer short-circuits between the backup lines
108
,
109
and the drain bus lines
103
, thereby creating conditions in which additional defects may occur.
Moreover, the location where the repair is performed is relatively distant from where the actual defect is located, and therefore, a highly accurate and expensive apparatus for removing the substrate is required

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