Repairable ROM array

Details Repairable ROM array Repairable ROM array

1983-10-24

1986-07-15

Harkcom, Gary V.

Excavating

371 21, 371 30, G06F 1122

Patent

active

046010319

ABSTRACT:
The individual rows of a ROM array are accessed by a row decoder/driver in response to the arrival of the address of the individual row on the address lines. A plurality of programmable switches store the address of a row of ROM array found to contain one or more defects. If the incoming address is that of the defective row each of a plurality of comparators connected to both an address line and the associated switch outputs a coincidence signal to an AND gate. The output of the AND gate accesses a spare row of RAM which thus replaces the defective row of the ROM array. Access to the spare row is automatic upon receipt of the address of the defective row. Each column of the ROM array contains a check bit computed from the remaining contents of the respective column, and the data to be stored in the spare row is generated from the remaining contents of the ROM array. At initialization, the generated data which should have been stored in the defective row is written into the spare row.

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Sakalay, "Correction of Bad Bits in a Memory Matrix", IBM Technical Disclosure Bulletin, vol. 6, No. 10, Mar. 1980, pp. 1-2.

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