Repairable multi-level overlay system for semiconductor device

Details Repairable multi-level overlay system for semiconductor device Repairable multi-level overlay system for semiconductor device

1982-07-08

1985-10-22

Edlow, Martin H.

Electricity: conductors and insulators

Feedthrough or bushing

Compression

357 81, 357 74, 357 75, 174 685, 361395, 361397, 361414, H01L 2712

Patent

active

045492000

ABSTRACT:
A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.

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Ecker et al., IBM TDB, vol. 22, No. 11, Apr. 80, p. 4852, "Low Profile . . . Means".

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