Reorder buffer circuit accommodating special instructions operat

Details Reorder buffer circuit accommodating special instructions operat Reorder buffer circuit accommodating special instructions operat

1996-03-29

1998-03-10

Lall, Parshotam S.

395393, 395800, G06F 930

Patent

active

057271771

ABSTRACT:
A superscalar processor provides register renaming using a reorder buffer includes special registers for handling predefined special instructions that operate on an odd-width data word. The superscalar processor includes a reorder buffer which stores result data having a predetermined standard bit-width. One or more instructions that generally occur only occasionally have a result data width that is substantially larger than the standard bit-width. The reorder buffer stores data of the standard bit-width and the occasional large bit-width in a storage that includes a plurality of standard-width storage elements in a first-in-first-out FIFO reorder buffer queue and a separate buffer that is specifically allocated for storing an extended result element. An extended result element includes a portion of a large bit-width result in excess of the standard bit-width result size.

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Advanced Micro Devices, Inc., RISC Design-Made Easy Application Guide, 1992.
Advanced Micro Devices, Inc., Am29050 Microprocessor User's Manual, 1991.
Mike Johnson, Superscalar Microprocessor Design, pp.127-146, Prentice Hall, Englewood Cliffs, New Jersey, 07632.

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