Reorder buffer architecture for accessing partial word operands

Details Reorder buffer architecture for accessing partial word operands Reorder buffer architecture for accessing partial word operands

1997-04-15

1999-07-27

Donaghue, Larry D.

395394, 395386, G06F 938

Patent

active

059305215

ABSTRACT:
A reorder buffer for an out-of-order issue/execute superscalar microprocessor is composed of a destination register unit, four data units, and a destination tag unit. The destination register and tag units are each made up of content addressable memory shift registers, while the data units are made up of random access memory shift registers which contain partial word operands. When an instruction is decoded, the destination register and tag units generate read and write match signals, respectively, for the data registers. The data registers are associated with corresponding lookup circuits and read/write driver cells. A valid bit is derived from a result byte input, and is used to selectively enable the lookup circuits and read/write driver cells to access the partial word operands in the data registers. Thus, the valid bit, in combination with the read and write match signals, provides the inventive reorder buffer with the ability to independently execute partial word operands in parallel.

REFERENCES:
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5134561 (1992-07-01), Liptay
patent: 5345569 (1994-09-01), Tran
patent: 5446912 (1995-08-01), Colwell et al.
patent: 5524263 (1996-06-01), Griffith et al.
patent: 5590392 (1996-12-01), Zuraski, Jr. et al.
patent: 5778245 (1998-07-01), Papworth et al.
Wallace et al. Design and Implementation of a 100MHz Reorder Buffer pp. 1-4 Aug. 1994.
Mike Johnson, Prentice Hall 1991; Superscalar Microprocessor Design. pp. 48-50; 92-94; 110; and 166-169.

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