Computer graphics processing and selective visual display system – Computer graphics processing – Graph generating
Reexamination Certificate
2000-06-01
2001-09-18
Nguyen, Phu K. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Graph generating
Reexamination Certificate
active
06292196
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a rendering processor for generating data to be displayed on a display device of a display control apparatus such as a CRT display, and in particular, to a hardware system for generating images and three-dimensional data at a high speed, The present invention further relates to an apparatus which displays on a display an image with gradation generated by the rendering processor, and in particular, to an apparatus for displaying on a display images having different lightness or luminance levels for the respective pixels associated with influence from illuminated light and the like.
Conventionally, for apparatuses to effect a display control, particularly to execute drawing processing, there have been proposed many processing systems.
For example, the Japanese Patent Unexamined Publication No. 59-229669 describes an example of processing to rotate an image in which coordinate values of a destination image are obtained corresponding to coordinates of lattice points of a source image. In this method, there does not appear any trouble if a DDA circuit for a line expansion is provided only for the (X, Y) coordinates of the destination; however, there actually exists problems that the processing performance is determined depending on the size of an image on the source side and that images of different lattice points are written or are not written at a destination lattice point many times in some cases.
The Japanese Patent Examined Publication No. 57-57715 describes a method in which gradation of each pixel is attained in a triangle for which a gradation value is beforehand assigned to a vertex of the triangle. According to this method, a shading operation on a graphic image is accomplished by a hardware system; however, since a memory access is necessary for each generation of a pixel, particularly, in the shading operation to general pixels in a direction parallel to the raster, there arises a problem related to the processing performance.
The Japanese Patent Unexamined Publication No. 60-252394 discloses a patent related to a color image display apparatus, and particularly, to a color image display apparatus including a variable configuration of memory planes. In this method, the bus configuration with respect to the CPU can be kept unchanged regardless of the number of memory planes; however, there is not provided an independent arithmetic circuit for each memory plane, which leads to a problem of performance associated with operations, for example, for the image processing.
The prior art technologies above aim at a high-speed processing for a partial processing of the graphic or image processing, namely, the inventions are to be implemented only either in the graphic processing of the image processing.
However, since sophisticated or developed functions, a higher precision, and an expansion of the display screen are desired in the screen display operation, it is necessary to satisfy the requirements above and at the same time to reduce the response time for the screen display operation.
Furthermore, in order to effect a high-speed processing of a color image, there has been disclosed, for example, “an apparatus for accessing an image memory” in the Japanese Patent Application No. 59-30278 in which an arithmetic unit is disposed for each plane of the frame memory so as to effect a concurrent processing. However, in this prior art technology, a comprehensive arithmetic system sufficiently processing an image with gradation has not been considered; consequently, if it is desired to execute a gradation change processing to alter gradation of an image, the host processor (CPU) is required to achieve again a computation of the image, which leads to a problem that the real time change of the display cannot be carried out.
Next, referring to drawings, a detailed description will be given of requirements of application to clarify the problem above.
As shown in
FIG. 27
, image data A on the left-hand side is defined with gradation in a two-dimensional plane. When the image data A is subjected to a texture mapping processing to apply the image data A on the entire surfaces of a rectangle parallel-piped as shown on the right-hand side so as to configure an image B, an image like an actual scene cannot be attained unless the mapping (image conversion or transform) is accomplished so as to develop a gradation difference between the rear side and the front side of the plane (or between the deeper side and the near side viewed from the side of the eyes of the user). Consequently, a higher density is assigned to the front side and a lower density is assigned to the rear side.
To implement this processing, for example, for pixels to be mapped onto the rear side, the value of each pixel of the gradation image on the two-dimensional plane are multiplied by 0.6 for the mapping operation; whereas for pixels to be mapped onto the front side, the value of each pixel of the gradation image on the two-dimensional plane are multiplied by 1.0 for the mapping operation; moreover, each pixel between the rear and front sides are required to be multiplied by (0.6-1.0) so as to take an intermediate value. As a result, the density of the portion of the image on the rear side becomes thinner than the original density thereof on the two-dimensional plane.
The density conversion in this processing is achieved by a host processor and hence a real time processing of the density conversion cannot be easily accomplished.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a rendering processor in which a DDA control circuit mainly effecting a line expansion for graphics is connected to a raster operation hardware for an image so as to achieve the rendering processing of images and graphics at a high speed.
Another object of the present invention is to provide a rendering processor which minimizes the response time in the screen display operation and which can cope with development of the function and increase in the precision of the screen display operation.
Further another object of the present invention is to provide processor elements of a rendering processor which is suitable for increasing the precision of the screen display operation.
Still another operation of the present invention is to provide a screen display controller which minimizes the response time of the screen display operation so as to develop a satisfactory operability.
Further another object of the present invention is to provide a display device in which luminance information of each gradation pixel undergoes an arithmetic processing so as to attain gradation images with different gradation levels on a display screen.
According to the present invention, there is provided an apparatus including a plurality of DDA control circuits wherein in each of the DDA circuits, coordinates of a source image, coordinates of a destination image, and gradation values associated therewith are computed so as to generate source and destination data to be supplied to a raster arithmetic unit depending on the computation result, thereby effecting a control of the arithmetic unit to obtain a plurality of pixels during a memory access and to effect a write operation thereof, which enables image and graphic processing to be achieved at a high speed.
In the DDA control circuits, there is disposed a hardware unit which can simultaneously generate the X-coordinate values of the source image, (X, Y) coordinate values of the destination image, the gradation values and Z-axis coordinate values of the destination image. Depending on the values thus attained, means for generating raster information including 16 pixels to be written and for detecting a separation point of the 16 pixels controls an access to a frame memory such that data comprising up to 16 pixels can be written in the memory by a frame memory access.
According to the present invention, the reduction of the response time in the screen display operation as well as the development of the function and increase in the preci
Fujita Ryo
Fukunaga Yasushi
Kato Takeshi
Koga Kazuyoshi
Yasuda Isao
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Phu K.
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